RZ_T2M中文资料瑞萨数据手册PDF规格书

■ On-chip 32-bit Arm Cortex-R52 processor

● High-speed realtime control with operating frequency of

200/400/800 MHz

● On-chip Dual/Single 32-bit Arm Cortex-R52 (revision r1p2)

● Tightly coupled memory (TCM) with ECC

– CPU0: 512 KB/64 KB

– CPU1: No support

● Instruction cache/data cache with ECC

– CPU0: 16 KB per cache

– CPU1: 32 KB per cache

● High-speed interrupt

● The FPU supports addition, subtraction, multiplication, division,

multiply-and-accumulate, and square-root operations at singleprecision

and double-precision.

● The NEON, Advanced SIMD, supports integer or single precision

results.

● Harvard architecture with 8-stage pipeline

● Supports the memory protection unit (MPU)

● Arm CoreSight architecture, includes support for debugging

through JTAG and SWD interfaces.

● No DCLS (Dual Core Lock Step) support

■ Low power consumption

● Standby mode and module stop function

■ On-chip SRAM

● 2.0 MB/1.5 MB of the on-chip SRAM with ECC

● 150/200 MHz

■ Data transfer

● DMAC: 16 channels × 2 units

■ Event link controller

● Module operations can be started by event signals rather than by

interrupt handlers.

● Linked operation of modules is available even while the CPU is in

the standby state.

■ Reset and power supply voltage control

● Five reset sources including a pin reset

■ Clock functions

● External clock/oscillator input frequency: 25 MHz

● CPU clock frequency: 200/400/800 MHz or 150/300/600 MHz

● System clock frequency: 200 MHz or 150 MHz

● Low-speed on-chip oscillator (LOCO): 240 kHz

■ Safety functions

● Register write protection, input clock oscillation stop detection and

CRC

● Master Memory Protection Unit (MPU)

■ Security functions (optional)

● Boot mode with security through encryption

● JTAG authentication

● Cryptologic accelerator

● TRNG

■ Encoder interfaces (optional)

● 2 channels

● EnDat 2.2, BiSS-C, FA-CODER, A-format, and HIPERFACE

DSL-compliant interfaces

● Frequency-divided output from an encoder