RTL8198中文资料IEEE 802.11n GIGABIT ETHERNET AP/ROUTER NETWORK PROCESSOR数据手册Realtek规格书

描述 Description

General Description
The RTL8198 is an integrated System-on-a-Chip (SoC) Application Specific Integrated Circuit (ASIC) that implements a L2 switch, L3 routing, and L4 NAT functions. An RLX5281 CPU is embedded and the clock rate can be up to 500MHz. To improve computational performance, a 16-Kbyte I-Cache, 8-Kbyte D-Cache, 40-K I-MEM, and 8-Kbyte D-MEM are provided. A standard 5-signal P1149.1 compliant EJTAG test interface is supported for CPU testing and software development.

特性 Features

■ SOC
   ◆ Embedded RISC CPU, RLX5281 with
      16K I-Cache, 8K D-Cache, 40K I-MEM,
      8K D-MEM
   ◆ Supports MIPS-1 ISA, MIPS16 ISA
   ◆ Clock rate up to 500MHz
   ◆ Provides a standard 5-signal P1149.1
      EJTAG test port
   ◆ Supports RLX5281 CPU suspend mode
■ L2 Capabilities
   ◆ Six Gigabit Ethernet MACs switch with
      five IEEE 802.3 10/100/1000Mbps
      physical layer transceivers
   ◆ Supports 1 dedicated GMII/RGMII/MII
      port to connect to an external MAC or
      PHY (supports both PHY mode and
      MAC mode) for HomePlug or
      HomePNA applications on RTL8198
   ◆ Non-blocking wire-speed reception and
      transmission and non-head-of-line
      blocking/forwarding
   ◆ Internal 512Kbit SRAM for packet
      buffering
   ◆ Internal 1024 entry 4-way hash L2 look
      up table
   ◆ Supports source and destination MAC
      address filtering
   ◆ Three LED indicators per port for link,
      speed, full/half duplex
   ◆ Bi-color LED display mode
■ CPU Interface (NIC)
   ◆ Supports BSD mbuf-like packet structure
      with adjustable cluster size (128-byte to
      2Kbyte) to provide optimum memory
      utilization
   ◆ The NIC DMA support multiple
      descriptor-ring architecture for QoS
      applications (supports 6 RX descriptor
      rings and 2 TX descriptor rings)
■ Peripheral Interfaces
   ◆ Supports PCI Express Host with
      integrated PHY to connect up to two
      master devices
   ◆ Two PCI Express PHY embedded
   ◆ Supports one USB 2.0 host controller
      for access to USB-supported peripherals
   ◆ One USB PHY is embedded
   ◆ Supports two 16550 UARTs
   ◆ Supports up to 44 GPIO pins
■ Memory Interfaces
   ◆ Serial Flash (SPI Type)
      ■ Supports two banks and dual I/O
         channels for SPI Flash application
      ■ Each Flash bank could be configured
         as 256K/512K/1M/2M/4M/8M/16M
         Bytes
      ■ Boot up from SPI flash is supported
   ◆ SDR DRAM
      ■ Supports two SDR DRAM banks;
         each can be configured as
         2M/4M/8M/16M/32M/64Mbyte
      ■ 16bit SDR DRAM data bus
         supported. System totally supports up
         to 128Mbyte SDR DRAM memory
         space
   ◆ DDR1 DRAM
      ■ Supports one DDR1 DRAM bank
         that can be configured as
         16M/32M/64M/128Mbytes
      ■ 16-bit DDR1 DRAM data bus
         supported. System totally supports up
         to 128Mbyte DDR1 DRAM memory
         space
   ◆ DDR2 DRAM
      ■ Supports one DDR2 DRAM bank
         that can be configured as
         32M/64M/128Mbyte
      ■ 16-bit DDR2 DRAM data bus
         supported. System totally supports up
         to 128Mbyte DDR2 DRAM memory
         space
■ Supports Green Ethernet
   ◆ Cable length power saving
   ◆ Power down power saving
■ Supports pre-IEEE 802.3az Energy Efficient
   Ethernet ability for 1000Base-T, 100base
   TX in full duplex operation and 10base-T in
   full/half duplex mode
■ Other Add-on-Value Features
   ◆ Supports Link Down Power Saving in
      Ethernet PHYceivers
   ◆ Supports two hardware timers and one
      watchdog timer
   ◆ Per-port configurable auto-crossover
      function
   ◆ Built-in regulator controller
      ■ DDR1 DRAM to transform 3.3V to
         2.5V via an external BJT transistor
      ■ DDR2 DRAM to transform 3.3V to
         1.8V via an external BJT transistor
   ◆ Supports Non-Flash Boot Interface
      (NFBI)
   ◆ Single 25MHz crystal or 40MHz clock
      input
   ◆ LQFP216-E-PAD package