RMQCEA3636DGBA-182中文资料36-Mbit DDR™ II+ SRAM 2-word Burst Architecture (2.5 Cycle Read latency) with ODT数据手册Renesas规格书

描述 Description

The RMQCEA3636DGBA is a 1, 048, 576-word by 36-bit and the RMQCEA3618DGBA is a 2, 097, 152-word by 18-bit synchronous quad data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell. It integrates unique synchronous peripheral circuitry and a burst counter. All input registers are controlled by an input clock pair (K and /K) and are latched on the positive edge of K and /K. These products are suitable for applications which require synchronous operation, High-Speed, low voltage, high density and wide bit configuration. These products are packaged in 165-pin plastic FBGA package.

特性 Features

• Power Supply 1.8 V for core (VDD), 1.4 V to VDD for I/O (VDDQ)
• Clock Fast clock cycle time for high bandwidth Two input clocks (K and /K) for precise DDR timing at clock rising edges only Two output echo clocks (CQ and /CQ) simplify data capture in high-speed systems Clock-stop capability with µs restart
• I/O Common data input/output bus Pipelined double data rate operation HSTL I/O User programmable output impedance PLL circuitry for wide output data valid window and future frequency scaling Data valid pin (QVLD) to indicate valid data on the output
• Function Two-tick burst for low DDR transaction size Internally self-timed write control Simple control logic for easy depth expansion JTAG 1149.1 compatible test access port
• Package 165 FBGA package (13 x 15 x 1.4 mm)