RM48L950DPGETG4中文资料德州仪器数据手册PDF规格书

1.1 Features 1

• High-Performance Microcontroller for Safety-

Critical Applications

– Dual CPUs Running in Lockstep

– ECC on Flash and RAM Interfaces

– Built-In Self-Test (BIST) for CPU and On-chip

RAMs

– Error Signaling Module With Error Pin

– Voltage and Clock Monitoring

• ARM® Cortex®-R4F 32-Bit RISC CPU

– Efficient 1.66 DMIPS/MHz With 8-Stage Pipeline

– FPU With Single- and Double-Precision

– 12-Region Memory Protection Unit (MPU)

– Open Architecture With Third-Party Support

• Operating Conditions

– System Clock up to 200 MHz

– Core Supply Voltage (VCC): 1.2 V Nominal

– I/O Supply Voltage (VCCIO): 3.3 V Nominal

– ADC Supply Voltage (VCCAD): 3.0 to 5.25 V

• Integrated Memory

– 3MB of Program Flash With ECC (RM48L950)

– 2MB of Program Flash With ECC

(RM48L750/550)

– 256KB of RAM With ECC (RM48L950/750)

– 192KB of RAM With ECC (RM48L550)

– 64KB of Flash With ECC for Emulated

EEPROM

• 16-Bit External Memory Interface

• Common Platform Architecture

– Consistent Memory Map Across Family

– Real-Time Interrupt (RTI) Timer OS Timer

– 96-Channel Vectored Interrupt Module (VIM)

– 2-Channel Cyclic Redundancy Checker (CRC)

• Direct Memory Access (DMA) Controller

– 16 Channels and 32 Peripheral Requests

– Parity Protection for Control Packet RAM

– DMA Accesses Protected by Dedicated MPU

• Frequency-Modulated Phase-Locked Loop

(FMPLL) With Built-In Slip Detector

• Separate Nonmodulating PLL

• Trace and Calibration Capabilities

– Embedded Trace Macrocell (ETM-R4)

– Data Modification Module (DMM)

– RAM Trace Port (RTP)

– Parameter Overlay Module (POM)

• Multiple Communication Interfaces

– 10/100 Mbps Ethernet MAC (EMAC)

• IEEE 802.3 Compliant (3.3-V I/O Only)

• Supports MII, RMII, and MDIO

– USB

• 2-Port USB Host Controller

• One Full-Speed USB Device Port

– Three CAN Controllers (DCANs)

• 64 Mailboxes, Each With Parity Protection

• Compliant to CAN Protocol Version 2.0B

– Standard Serial Communication Interface (SCI)

– Local Interconnect Network (LIN) Interface

Controller

• Compliant to LIN Protocol Version 2.1

• Can be Configured as a Second SCI

– Inter-Integrated Circuit (I2C)

– Three Multibuffered Serial Peripheral Interfaces

(MibSPIs)

• 128 Words With Parity Protection Each

– Two Standard Serial Peripheral Interfaces

(SPIs)

• Two Next Generation High-End Timer (N2HET)

Modules

– N2HET1: 32 Programmable Channels

– N2HET2: 18 Programmable Channels

– 160-Word Instruction RAM Each With Parity

Protection

– Each N2HET Includes Hardware Angle

Generator

– Dedicated High-End Transfer Unit (HTU) With

MPU for Each N2HET

• Two 12-Bit Multibuffered ADC Modules

– ADC1: 24 Channels

– ADC2: 16 Channels Shared With ADC1

– 64 Result Buffers With Parity Protection Each

• General-Purpose Input/Output (GPIO) Pins

Capable of Generating Interrupts

– 16 Pins on the ZWT Package

– 10 Pins on the PGE Package

• IEEE 1149.1 JTAG, Boundary Scan and ARM

CoreSight™ Components

• JTAG Security Module

• Packages

– 144-Pin Quad Flatpack (PGE) [Green]

– 337-Ball Grid Array (ZWT) [Green]

1.2 Applications

• Industrial Safety Applications

– Industrial Automation

– Safe Programmable Logic Controllers (PLCs)

– Power Generation and Distribution

– Turbines and Windmills

– Elevators and Escalators

• Medical Applications

– Ventilators

– Defibrillators

– Infusion and Insulin Pumps

– Radiation Therapy

– Robotic Surgery

1.3 Description

The RM48Lx50 device is a high-performance microcontroller family for safety systems. The safety

architecture includes dual CPUs in lockstep, CPU and memory BIST logic, ECC on both the flash and the

data SRAM, parity on peripheral memories, and loopback capability on peripheral I/Os.

The RM48Lx50 device integrates the ARM Cortex-R4F Floating-Point CPU. The CPU offers an efficient

1.66 DMIPS/MHz, and has configurations that can run up to 200 MHz, providing up to 332 DMIPS. The

device supports the little-endian [LE] format.

The RM48L950 device has 3MB of integrated flash and 256KB of data RAM. The RM48L750 device has

2MB of integrated flash and 256KB of data RAM. The RM48L550 device has 2MB of integrated flash and

192KB of data RAM. Both the flash and RAM have single-bit error correction and double-bit error

detection. The flash memory on this device is a nonvolatile, electrically erasable, and programmable

memory implemented with a 64-bit-wide data bus interface. The flash operates on a 3.3-V supply input

(same level as I/O supply) for all read, program, and erase operations. When in pipeline mode, the flash

operates with a system clock frequency of up to 200 MHz. The SRAM supports single-cycle read and write

accesses in byte, halfword, word, and double-word modes.

The RM48Lx50 device features peripherals for real-time control-based applications, including two Next

Generation High-End Timer (N2HET) timing coprocessors and two 12-bit Analog-to-Digital Converters

(ADCs) supporting up to 24 inputs.

The N2HET is an advanced intelligent timer that provides sophisticated timing functions for real-time

applications. The timer is software-controlled, using a reduced instruction set, with a specialized timer

micromachine and an attached I/O port. The N2HET can be used for pulse-width-modulated outputs,

capture or compare inputs, or GPIO. The N2HET is especially well suited for applications requiring

multiple sensor information and drive actuators with complex and accurate time pulses. A High-End Timer

Transfer Unit (HTU) can perform DMA-type transactions to transfer N2HET data to or from main memory.

A Memory Protection Unit (MPU) is built into the HTU.

The device has two 12-bit-resolution MibADCs with 24 channels and 64 words of parity-protected buffer

RAM each. The MibADC channels can be converted individually or can be grouped by software for

sequential conversion sequences. Sixteen channels are shared between the two MibADCs. There are

three separate groupings. Each sequence can be converted once when triggered or configured for

continuous conversion mode. The MibADC has a 10-bit mode for use when compatibility with older

devices or faster conversion time is desired.

The device has multiple communication interfaces: three MibSPIs, two SPIs, one LIN, one SCI, three

DCANs, one I2C module, one Ethernet, and one USB module. The SPIs provide a convenient method of

serial high-speed communication between similar shift-register type devices. The LIN supports the Local

Interconnect standard 2.0 and can be used as a UART in full-duplex mode using the standard Non-

Return-to-Zero (NRZ) format.

The DCAN supports the CAN 2.0 (A and B) protocol standard and uses a serial, multimaster

communication protocol that efficiently supports distributed real-time control with robust communication

rates of up to 1 Mbps. The DCAN is ideal for systems operating in noisy and harsh environments (for

example, automotive vehicle networking and industrial fieldbus) that require reliable serial communication

or multiplexed wiring.

The Ethernet module supports MII, RMII, and MDIO interfaces.

The USB module includes a 2-port USB host controller. It is revision 2.0-compatible, based on the OHCI

specification for USB, release 1.0. The USB module also includes a USB device controller compatible with

the USB specification revision 2.0 and USB specification revision 1.1.

The I2C module is a multimaster communication module providing an interface between the

microcontroller and an I2C-compatible device through the I2C serial bus. The I2C supports speeds of 100

and 400 Kbps.