RM44L520数据手册TI中文资料规格书

描述 Description

The RM44Lx20 device is part of the Hercules RM series of high-performance industrial-gradeARM® Cortex®-R-based MCUs. Comprehensive documentation, tools, and softwareare available to assist in the development of IEC 61508 functionalsafety applications. Start evaluating today with the Hercules RM LaunchPad Development Kit. The RM44Lx20 device hason-chip diagnostic features including: dual CPUs in lockstep; CPU and memoryBuilt-In Self-Test (BIST) logic; ECC on both the flash and the SRAM; parityon peripheral memories; and loopback capability on most peripheral I/Os. The RM44Lx20 device integrates the ARM Cortex-R4F floating-point CPUwhich offers an efficient 1.66 DMIPS/MHz, and has configurations which canrun up to 180 MHz providing up to 298 DMIPS. The RM44Lx20 device supportsthe little-endian [LE] format. The RM44Lx20 device has up to 1MB of integrated flash and 128KB ofRAM configurations with single-bit error correction and double-bit errordetection. The flash memory on this device is nonvolatile, electricallyerasable and programmable, and is implemented with a 64-bit-wide data businterface. The flash operates on a 3.3-V supply input (same level as the I/Osupply) for all read, program, and erase operations. The SRAM supportssingle-cycle read and write accesses in byte, halfword, word, and doublewordmodes throughout the supported frequency range. The RM44Lx20 device features peripherals for real-time control-basedapplications, including two Next-Generation High-End Timer (N2HET) timingcoprocessors with up to 44 total I/O terminals, seven Enhanced PWM (ePWM)modules with up to 14 outputs, six Enhanced Capture (eCAP) modules, twoEnhanced Quadrature Encoder Pulse (eQEP) modules, and two 12-bitAnalog-to-Digital Converters (ADCs) supporting up to 24 inputs. The N2HET is an advanced intelligent timer that provides sophisticatedtiming functions for real-time applications. The timer issoftware-controlled, using a reduced instruction set, with a specializedtimer micromachine and an attached I/O port. The N2HET can be used forpulse-width-modulated outputs, capture or compare inputs, or general-purposeI/O (GIO). The N2HET is especially well suited for applications requiringmultiple sensor information and drive actuators with complex and accuratetime pulses. A High-End Timer Transfer Unit (HTU) can transfer N2HET data to orfrom main memory. A Memory Protection Unit (MPU) is built into the HTU. The ePWM module can generate complex pulse width waveforms with minimalCPU overhead or intervention. The ePWM is easy to use and supportscomplementary PWMs and deadband generation. With integrated trip zoneprotection and synchronization with the on-chip MibADC, the ePWM is idealfor digital motor control applications. The eCAP module is essential in systems where the accurately timed captureof external events is important. The eCAP can also be used to monitor theePWM outputs or to generate simple PWM when not needed for captureapplications. The eQEP module is used for direct interface with a linear or rotaryincremental encoder to get position, direction, and speed information from arotating machine as used in high-performance motion and position-controlsystems.The device has two 12-bit-resolution MibADCs with 24 total inputs and 64words of parity-protected buffer RAM each. The MibADC channels can beconverted individually or can be grouped by software for sequentialconversion sequences. Sixteen inputs are shared between the two MibADCs. Thereare three separate groups. Each group can be converted once when triggeredor configured for continuous conversion mode. The MibADC has a 10-bit modefor use when compatibility with older devices or faster conversion time isdesired.The device has multiple communication interfaces: three MibSPIs; two SPIs;two SCIs, one of which can be used as LIN; up to three DCANs; and one I2Cmodule. The SPI provides a convenient method of serial interaction forhigh-speed communications between similar shift-register type devices. TheLIN supports the Local Interconnect standard 2.0 and can be used as a UARTin full-duplex mode using the standard Non-Return-to-Zero (NRZ) format. TheDCAN supports the CAN 2.0B protocol standard and uses a serial, multimastercommunication protocol that efficiently supports distributed real-timecontrol with robust communication rates of up to 1 Mbps. The DCAN is idealfor applications operating in noisy and harsh environments (for example,automotive and industrial fields) that require reliable serial communication ormultiplexed wiring. The I2C module is a multimaster communication module providing aninterface between the microcontroller and an I2C-compatibledevice through the I2C serial bus. The I2C module supports speedsof 100 and 400 kbps. A Frequency-Modulated Phase-Locked Loop (FMPLL) clock module is used tomultiply the external frequency reference to a higher frequency for internaluse. The FMPLL provides one of the six possible clock source inputs to theGlobal Clock Module (GCM). The GCM manages the mapping between the availableclock sources and the device clock domains. The device also has an external clock prescaler (ECP) circuit that whenenabled, outputs a continuous external clock on the ECLK terminal. The ECLKfrequency is a user-programmable ratio of the peripheral interface clock (VCLK) frequency. This low-frequency output can be monitored externally as anindicator of the device operating frequency. The Direct Memory Access (DMA) controller has 16 channels, 32 peripheralrequests, and parity protection on its memory. An MPU is built into the DMAto protect memory against erroneous transfers. The Error Signaling Module (ESM) monitors device errors and determineswhether an interrupt or external error signal (nERROR) is asserted when afault is detected. The nERROR terminal can be monitored externally as anindicator of a fault condition in the microcontroller. With integrated functional safety features and a wide choice of communicationand control peripherals, the RM44Lx20 device is an ideal solution forhigh-performance, real-time control applications with safety-critical

特性 Features

• High-Performance Microcontroller (MCU) for Safety-Critical Applications
• Dual CPUs Running in Lockstep
• ECC on Flash and RAM Interfaces
• Built-In Self-Test (BIST) for CPU and On-chip RAMs
• Error Signaling Module With Error Pin
• Voltage and Clock Monitoring

• ARM Cortex-R4F 32-Bit RISC CPU
• 1.66 DMIPS/MHz With 8-Stage Pipeline
• FPU With Single and Double Precision
• 12-Region Memory Protection Unit (MPU)
• Open Architecture With Third-Party Support

• Operating Conditions
• Up to 180-MHz System Clock
• Core Supply Voltage (VCC): 1.14 to 1.32 V
• I/O Supply Voltage (VCCIO): 3.0 to 3.6 V

• Integrated Memory
• Up to 1MB of Flash With ECC
• 128KB of RAM With ECC
• 64KB of Flash for Emulated EEPROM With ECC

• Common Platform Architecture
• Consistent Memory Map Across Family
• Real-Time Interrupt Timer (RTI) OS Timer
• 128-Channel Vectored Interrupt Module (VIM)
• 2-Channel Cyclic Redundancy Checker (CRC)

• Direct Memory Access (DMA) Controller
• 16 Channels and 32 Peripheral Requests
• Parity for Control Packet RAM
• DMA Accesses Protected by Dedicated MPU

• Frequency-Modulated Phase-Locked Loop (FMPLL) With Built-In Slip Detector
• IEEE 1149.1 JTAG, Boundary Scan and ARM CoreSight Components
• Advanced JTAG Security Module (AJSM)
• Up to 64 General-Purpose I/O (GIO) Pins
• Up to 16 GIO Pins With Interrupt Generation Capability

• Enhanced Timing Peripherals
• 7 Enhanced Pulse Width Modulator (ePWM) Modules
• 6 Enhanced Capture (eCAP) Modules
• 2 Enhanced Quadrature Encoder Pulse (eQEP) Modules

• Two Next Generation High-End Timer (N2HET) Modules
• N2HET1: 32 Programmable Channels
• N2HET2: 18 Programmable Channels
• 160-Word Instruction RAM With Parity Protection Each
• Each N2HET Includes Hardware Angle Generator
• Dedicated High-End Timer Transfer Unit (HTU) for Each N2HET

• Two 12-Bit Multibuffered ADC Modules
• ADC1: 24 Channels
• ADC2: 16 Channels
• 16 Shared Channels
• 64 Result Buffers With Parity Protection Each

• Multiple Communication Interfaces
• Up to Three CAN Controllers (DCANs)
• 64 Mailboxes With Parity Protection Each
• Compliant to CAN Protocol Version 2.0A and 2.0B

• Inter-Integrated Circuit (I2C)
• 3 Multibuffered Serial Peripheral Interfaces (MibSPIs)
• 128 Words With Parity Protection Each
• 8 Transfer Groups

• One Standard Serial Peripheral Interface (SPI) Module
• Two UART (SCI) Interfaces, One With Local Interconnect Network (LIN 2.1) Interface Support

• Packages
• 144-Pin Quad Flatpack (PGE) [Green]
• 100-Pin Quad Flatpack (PZ) [Green]