RCLAMP3346PQ电路保护的TVS-二极管规格书PDF中文资料

描述 Description

The RClamp®3346PQ provides ESD protection for

highspeed data interfaces. It features a high maximum

ESD withstand voltage of ±17kV contact and ±20kV

air discharge per IEC 61000-4-2. RClamp3346PQ is

designed to minimize both the ESD peak clamping and

the TLP clamping. Package inductance is reduced at

each pin resulting in lower peak ESD clamping voltage.

The dynamic resistance is among the industry’s lowest

at 0.15 Ohms (typical). Maximum capacitance on each

line to ground is 0.65pF allowing the RClamp3346PQ to

be used in applications operating in excess of 5GHz

without signal attenuation. Each device will protect up

to six lines (three high-speed pairs).

The RClamp3346PQ is in a 7-pin SGP2708N7 package

measuring 2.7 x 0.8mm with a nominal height of

0.50mm. The leads have a nominal pin-to-pin pitch of

0.40mm. Flow- through package design simplifies PCB

layout and maintains signal integrity on high-speed lines.

The combination of low peak ESD clamping, low

dynamic resistance, and innovative package design

enables this device to provide the highest level of ESD

protection for applications such as USB 3.0, eSATA, and

DisplayPort.

特性 Features

• ESD protection for high-speed data lines to

ŒŒ IEC 61000-4-2 (ESD) +/-17kV (Contact), +/- 20 kV (Air)

ŒŒ IEC 61000-4-5 (Lightning) 4.5A (8/20 μs)

ŒŒ IEC 61000-4-4 (EFT) 40A (5/50ns)

• Package design optimized for high speed lines

• Flow-Through design

• Protects six high-speed lines

• Low capacitance: 0.65pF Maximum (I/O to Ground)

• Low ESD clamping voltage

• Low dynamic resistance: 0.15 Ohms (Typical)

• Qualified to AEC-Q100, Grade 1

• Solid-state silicon-avalanche technology

Mechanical Characteristics

• SGP2708N7 7-pin package (2.7 x 0.8 x 0.50mm)

• Pb-Free, Halogen Free, RoHS/WEEE compliant

• Lead Pitch: 0.4mm (intra-pair)

• Lead Finish: NiPdAu

• Marking: Marking code

• Packaging: Tape and Reel

Applications

• USB 3.0

• eSATA

• Display Port

• LVDS