RC32508A中文资料FemtoClock 2 Jitter Attenuator or Clock Generator数据手册Renesas规格书

描述 Description

The RC32508A regenerates and distributes ultra-low jitter clock outputs and features up to 2 independent frequency domains that can be either locked to the external reference clock or locked to a free-run crystal or oscillator. Digital PLL (DPLL) support hitless reference switching between references from redundant timing sources. The device supports multiple independent timing channels for clock generation and jitter attenuation for high-speed serial links. Input-to-input, input-to-output and output-to-output phase skew can all be precisely managed.  The device outputs ultra-low-jitter clocks that can directly synchronize SERDES running at up to 112Gbps; as well as CPRI/OBSAI, SONET/SDH ADC/DAC. The device is ideal for use in 100G/200G/400G/800G telecom switch line cards, fabric cards and OTN applications.

特性 Features

• Can be configured as clock generator or jitter attenuator/synchronizer
• Low power, less than 0.8W typical
• Low jitter, less than 50fs-RMS
• Compliant with ITU-T G.8262 & G.8262.1 option 1 and 2 for synchronous Ethernet Equipment Clock (EEC/eEEC) without degrading output jitter
• Jitter attenuation with programmable loop bandwidth from 0.1Hz to 12kHz
• Up to 2 independent frequency domains and 8 integer output dividers
• Each frequency domain can be slaved with DPLL or free-run
• DPLL can be configured as DCO
• LVCMOS, AC-LVPECL, AC-LVDS, HCSL, AC-CML output modes supported with programmable output swing
• Up to 2single ended or 1differential clock inputs, 1 crystal/XO/TCXO/OCXO input
• Supports 1MHz I2C, 400kHz SMBus or 50MHz SPI serial port
• Internal non-volatile memory (up to 8 different configurations) provides default device settings on power-up.
• 1.8V core and output operation
• -40° to +85°C industrial temperature operation