RC22112A数据手册Renesas中文资料规格书

描述 Description

The RC22112A regenerates and distributes ultra-low jitter clock outputs and features up to 6 independent frequency domains that can be locked to a free-run crystal or oscillator. The device supports multiple independent reference clocks for high-speed serial links. Input-to-input, input-to-output and output-to-output phase skew can all be precisely managed.  The device outputs ultra-low-jitter clocks that can directly synchronize SERDES running at up to 56Gbps. The device is ideal for use in 100G/200G/400G/800G telecom switch fabric cards and OTN applications.

特性 Features

• Low power, less than 1.4W typical
• Low jitter, less than 100 fs-RMS
• PCIe Gen 1-6 CC, SRIS and SRNS support
• Up to six fractional output dividers and 12 integer output dividers
• Each fractional output divider is free-run and locked to APLL
• Each fractional output divider can be configured as NCO or DCO
• LVCMOS, LVPECL, LVDS, HCSL, CML, SSTL, HSTL output modes supported with programmable output swing and common mode voltage
• One crystal/XO input
• Up to nine GPIO pins programmable to device select or system monitor options
• Supports 1MHz I2C, 400kHz SMBus, or 50MHz SPI serial port
• Internal non-volatile memory (up to 16 different configurations), or external serial I2C EEPROM provide default device settings on power-up.
• 2.5V and 3.3V core and 1.8V, 2.5V, and 3.3V output operation
• -40° to +85°C industrial temperature operation