VersaClock 7 Programmable Clock Generator Family

Features ▪ 169fs RMS phase jitter (10kHz - 20MHz, 156.25MHz) ▪ PCIe® Gen6 Common Clock (CC) 27fs RMS ▪ PCIe SRIS and SRNS support ▪ 1kHz to 650MHz LVDS/LP-HCSL outputs ▪ 1kHz to 200MHz LVCMOS outputs ▪ Simple AC-coupling to LVPECL and CML ▪ LP-HCSL integrates 100 or 85 terminations ▪ Pr

文件：1.90565 Mbytes 页数：59 Pages

RENESAS

瑞萨

VersaClock 7 Programmable Clock Generator Family

Features ▪ 169fs RMS phase jitter (10kHz - 20MHz, 156.25MHz) ▪ PCIe® Gen6 Common Clock (CC) 27fs RMS ▪ PCIe SRIS and SRNS support ▪ 1kHz to 650MHz LVDS/LP-HCSL outputs ▪ 1kHz to 200MHz LVCMOS outputs ▪ Simple AC-coupling to LVPECL and CML ▪ LP-HCSL integrates 100 or 85 terminations ▪ Pr

文件：1.90565 Mbytes 页数：59 Pages

RENESAS

瑞萨

VersaClock 7 Programmable Clock Generator Family

▪ 169fs RMS phase jitter at 156.25MHz (typ.) ▪ PCIe® Gen7 Common Clock jitter: 8fs RMS (typ.) ▪ PCIe SRIS and SRNS support ▪ 1kHz to 200MHz LVCMOS outputs ▪ 1kHz to 650MHz LVDS/LP-HCSL outputs ▪ LP-HCSL integrates 100 or 85 terminations ▪ Simple AC-coupling to LVPECL and CML ▪ Programmabl

文件：1.86301 Mbytes 页数：61 Pages

RENESAS

瑞萨

VersaClock 7 Programmable Clock Generator Family

▪ 169fs RMS phase jitter at 156.25MHz (typ.) ▪ PCIe® Gen7 Common Clock jitter: 8fs RMS (typ.) ▪ PCIe SRIS and SRNS support ▪ 1kHz to 200MHz LVCMOS outputs ▪ 1kHz to 650MHz LVDS/LP-HCSL outputs ▪ LP-HCSL integrates 100 or 85 terminations ▪ Simple AC-coupling to LVPECL and CML ▪ Programmabl

文件：1.86301 Mbytes 页数：61 Pages

RENESAS

瑞萨

VersaClock 7 Programmable Clock Generator Family

▪ 169fs RMS phase jitter at 156.25MHz (typ.) ▪ PCIe® Gen7 Common Clock jitter: 8fs RMS (typ.) ▪ PCIe SRIS and SRNS support ▪ 1kHz to 200MHz LVCMOS outputs ▪ 1kHz to 650MHz LVDS/LP-HCSL outputs ▪ LP-HCSL integrates 100 or 85 terminations ▪ Simple AC-coupling to LVPECL and CML ▪ Programmabl

文件：1.86304 Mbytes 页数：61 Pages

RENESAS

瑞萨

VersaClock 7 Programmable Clock Generator Family

▪ 169fs RMS phase jitter at 156.25MHz (typ.) ▪ PCIe® Gen7 Common Clock jitter: 8fs RMS (typ.) ▪ PCIe SRIS and SRNS support ▪ 1kHz to 200MHz LVCMOS outputs ▪ 1kHz to 650MHz LVDS/LP-HCSL outputs ▪ LP-HCSL integrates 100 or 85 terminations ▪ Simple AC-coupling to LVPECL and CML ▪ Programmabl

文件：1.86304 Mbytes 页数：61 Pages

RENESAS

瑞萨

VersaClock 7 Programmable Clock Generator Family

▪ 169fs RMS phase jitter at 156.25MHz (typ.) ▪ PCIe® Gen7 Common Clock jitter: 8fs RMS (typ.) ▪ PCIe SRIS and SRNS support ▪ 1kHz to 200MHz LVCMOS outputs ▪ 1kHz to 650MHz LVDS/LP-HCSL outputs ▪ LP-HCSL integrates 100 or 85 terminations ▪ Simple AC-coupling to LVPECL and CML ▪ Programmabl

文件：1.86301 Mbytes 页数：61 Pages

RENESAS

瑞萨

VersaClock 7 Programmable Clock Generator Family

▪ 169fs RMS phase jitter at 156.25MHz (typ.) ▪ PCIe® Gen7 Common Clock jitter: 8fs RMS (typ.) ▪ PCIe SRIS and SRNS support ▪ 1kHz to 200MHz LVCMOS outputs ▪ 1kHz to 650MHz LVDS/LP-HCSL outputs ▪ LP-HCSL integrates 100 or 85 terminations ▪ Simple AC-coupling to LVPECL and CML ▪ Programmabl

文件：1.86301 Mbytes 页数：61 Pages

RENESAS

瑞萨

VersaClock 7 Programmable Clock Generator Family

▪ 169fs RMS phase jitter at 156.25MHz (typ.) ▪ PCIe® Gen7 Common Clock jitter: 8fs RMS (typ.) ▪ PCIe SRIS and SRNS support ▪ 1kHz to 200MHz LVCMOS outputs ▪ 1kHz to 650MHz LVDS/LP-HCSL outputs ▪ LP-HCSL integrates 100 or 85 terminations ▪ Simple AC-coupling to LVPECL and CML ▪ Programmabl

文件：1.86301 Mbytes 页数：61 Pages

RENESAS

瑞萨

VersaClock 7 Programmable Clock Generator Family

▪ 169fs RMS phase jitter at 156.25MHz (typ.) ▪ PCIe® Gen7 Common Clock jitter: 8fs RMS (typ.) ▪ PCIe SRIS and SRNS support ▪ 1kHz to 200MHz LVCMOS outputs ▪ 1kHz to 650MHz LVDS/LP-HCSL outputs ▪ LP-HCSL integrates 100 or 85 terminations ▪ Simple AC-coupling to LVPECL and CML ▪ Programmabl

文件：1.86301 Mbytes 页数：61 Pages

RENESAS

瑞萨