R5F566TKCDFB中文资料瑞萨数据手册PDF规格书

■ 32-bit RXv3 CPU core

 Maximum operating frequency: 160 MHz

Capable of 928 CoreMark in operation at 160 MHz

 JTAG and FINE (one-line) debugging interfaces

■ Low-power design and architecture

 Operation from a single 2.7- to 5.5-V supply

 Four low-power modes

■ On-chip code flash memory

 Supports versions with 1 Mbytes/512 Kbytes/256 Kbytes

 No wait cycles at up to 120 MHz or when the ROM cache is hit

 User code is programmable by on-board or off-board programming.

■ On-chip data flash memory

 32 Kbytes, reprogrammable up to 100,000 times

 Programming/erasing as background operations (BGOs)

■ On-chip SRAM, no wait states

 128K/64 Kbytes of SRAM (no wait states)

 16 Kbytes of RAM with ECC (with wait)

■ Data transfer

 DMACa: 8 channels

 DTCa: 1 channel

■ ELC

 Module operation can be initiated by event signals without using

interrupts

 Linked operation between modules is possible when the CPU is in

sleep mode

■ Reset and supply management

 Power-on reset (POR)

 Low voltage detection (LVDA) with voltage settings

■ Clock functions

 Frequency of resonator for main clock oscillator: 8 to 24 MHz (this

can be used as the PLL reference clock)

 High-speed on-chip oscillator: 16 MHz/18 MHz/20 MHz (this can

be used as the PLL reference clock)

 Low-speed on-chip oscillator: 240 kHz

■ Independent watchdog timer

 120-kHz IWDT-dedicated on-chip oscillator clock operation

■ Useful functions for IEC60730 compliance

 Oscillation-stoppage detection, functions for self-diagnosis and

detection of disconnection for the A/D converter, clock frequency

accuracy measurement circuit, independent watchdog timer, RAM

test-assisting function by DOC, and CRCA, etc.

 Register write protection function can protect values in important

registers against overwriting.

■ External bus

 Bus clock at 40 MHz (max)

 Four CS areas

 8- or 16-bit bus space is selectable per area