GPIO for TSMC 16nm FF

Key Features  Support 1.8V IO and 3.3V/1.8V dual voltage IO with 1.8V device  Support SD Specifications 3.0 Interface  Programmable Output drivability, weak pull-up/pull-down  Minimized I/O size by optimized ESD structure  High reliability of ESD protection with Dual diode & RC Triggered

文件：189.31 Kbytes 页数：1 Pages

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1.8V Standard Cell for TSMC 28nm HPC

Key Features - 1.8VTr-cell is Low Leak very smaller than Core-Cells (5.6pA @2NAND) - Gate Delay: 20ps@2NAND@Slow Condition - Technology is TSMC 28nm HPC+. - Electrical characteristic

文件：178.84 Kbytes 页数：1 Pages

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3.0V Standard Cell for TSMC 40nm LP

- 3.0VTr-cell is Low Leak very smaller than Core-Cells (0.16pA @2NAND) - Gate Delay: 180ps@2NAND@Slow Condition] - Technology is TSMC 40nm LP. - Electrical characteristic

文件：183.36 Kbytes 页数：1 Pages

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32-bit RISC CPU

Key Features  RISC architecture  32 -bit general purpose register x 16  Number of instructions 83  5 stage pipeline  Two formats of 16 bit length instruction and 32 bit instruction are adopted  The code size of the program can be suppressed by the instruction format of 16 bit length

文件：98.39 Kbytes 页数：1 Pages

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Analog-PLL For Frequency Multiplying

文件：197.91 Kbytes 页数：1 Pages

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