LVCMOS Clock Generator

The QS5917T Clock Driver uses an internal phase locked loop (PLL) to lock low skew outputs to one of two reference clock inputs. Eight outputs are available: Q0-Q4, 2xQ, Q/2, Q5. Careful layout and design insures < 500ps skew between the Q0-Q4, and Q/2 outputs. The QS5917T includes an internal RC fi 5V operation\n2xQ output, Q/2 output, Q output\nOutputs tri-state while RST low\nInternal loop filter RC network\nLow noise TTL level outputs\n< 500ps output skew, Q0-Q4\nPLL disable feature for low frequency testing\nBalanced Drive Outputs ± 24mA\n132MHz maximum frequency (2xQ output)\nFunctional e;

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