丝印：PLL1707；Package：SSOP；3.3-V DUAL PLL MULTICLOCK GENERATOR

FEATURES 27-MHz Master Clock Input Generated Audio System Clock (PLL1707): – SCKO0: 768 fS (fS = 44.1 kHz) – SCKO1: 768 fS, 512 fS (fS = 48 kHz) – SCKO2: 256 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) – SCKO3: 384 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) Generated Audio System Clock (PLL170

文件：365.33 Kbytes 页数：25 Pages

TI

德州仪器

丝印：PLL1707I；Package：SSOP；3.3-V DUAL-PLL MULTICLOCK GENERATOR

1FEATURES • Qualified for Automotive Applications • 27-MHz Master Clock Input • Generated Audio System Clock – SCKO0: 768 fS (fS = 44.1 kHz) – SCKO1: 768 fS, 512 fS (fS = 48 kHz) – SCKO2: 256 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) – SCKO3: 384 f S (fS = 32, 44.1, 48, 64, 88.2, 96 kHz)

文件：830.92 Kbytes 页数：18 Pages

TI

德州仪器

丝印：PLL1707I；Package：SSOP；3.3-V DUAL-PLL MULTICLOCK GENERATOR

1FEATURES • Qualified for Automotive Applications • 27-MHz Master Clock Input • Generated Audio System Clock – SCKO0: 768 fS (fS = 44.1 kHz) – SCKO1: 768 fS, 512 fS (fS = 48 kHz) – SCKO2: 256 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) – SCKO3: 384 f S (fS = 32, 44.1, 48, 64, 88.2, 96 kHz)

文件：830.92 Kbytes 页数：18 Pages

TI

德州仪器

丝印：PLL1708；Package：SSOP；3.3-V DUAL PLL MULTICLOCK GENERATOR

FEATURES 27-MHz Master Clock Input Generated Audio System Clock (PLL1707): – SCKO0: 768 fS (fS = 44.1 kHz) – SCKO1: 768 fS, 512 fS (fS = 48 kHz) – SCKO2: 256 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) – SCKO3: 384 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) Generated Audio System Clock (PLL170

文件：365.33 Kbytes 页数：25 Pages

TI

德州仪器

丝印：PLL1708；Package：SSOP；3.3-V DUAL PLL MULTICLOCK GENERATOR

FEATURES 27-MHz Master Clock Input Generated Audio System Clock (PLL1707): – SCKO0: 768 fS (fS = 44.1 kHz) – SCKO1: 768 fS, 512 fS (fS = 48 kHz) – SCKO2: 256 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) – SCKO3: 384 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) Generated Audio System Clock (PLL170

文件：365.33 Kbytes 页数：25 Pages

TI

德州仪器

丝印：PLL1708；Package：SSOP；3.3-V DUAL PLL MULTICLOCK GENERATOR

FEATURES 27-MHz Master Clock Input Generated Audio System Clock (PLL1707): – SCKO0: 768 fS (fS = 44.1 kHz) – SCKO1: 768 fS, 512 fS (fS = 48 kHz) – SCKO2: 256 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) – SCKO3: 384 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) Generated Audio System Clock (PLL170

文件：365.33 Kbytes 页数：25 Pages

TI

德州仪器

丝印：PLL1708；Package：SSOP；3.3-V DUAL PLL MULTICLOCK GENERATOR

FEATURES 27-MHz Master Clock Input Generated Audio System Clock (PLL1707): – SCKO0: 768 fS (fS = 44.1 kHz) – SCKO1: 768 fS, 512 fS (fS = 48 kHz) – SCKO2: 256 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) – SCKO3: 384 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) Generated Audio System Clock (PLL170

文件：365.33 Kbytes 页数：25 Pages

TI

德州仪器

丝印：PLL1708；Package：SSOP；3.3-V DUAL PLL MULTICLOCK GENERATOR

FEATURES 27-MHz Master Clock Input Generated Audio System Clock (PLL1707): – SCKO0: 768 fS (fS = 44.1 kHz) – SCKO1: 768 fS, 512 fS (fS = 48 kHz) – SCKO2: 256 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) – SCKO3: 384 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) Generated Audio System Clock (PLL170

文件：365.33 Kbytes 页数：25 Pages

TI

德州仪器

丝印：PLL1708；Package：SSOP；3.3-V DUAL PLL MULTICLOCK GENERATOR

FEATURES 27-MHz Master Clock Input Generated Audio System Clock (PLL1707): – SCKO0: 768 fS (fS = 44.1 kHz) – SCKO1: 768 fS, 512 fS (fS = 48 kHz) – SCKO2: 256 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) – SCKO3: 384 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) Generated Audio System Clock (PLL170

文件：365.33 Kbytes 页数：25 Pages

TI

德州仪器

Cyclone III Device Handbook

Cyclone III Device Family Overview Cyclone® III device family offers a unique combination of high functionality, low power and low cost. Based on Taiwan Semiconductor Manufacturing Company (TSMC) low-power (LP) process technology, silicon optimizations and software features to minimize power cons

文件：7.30201 Mbytes 页数：274 Pages

Altera

阿尔特