PIC32MX570F512L中文资料PIC 32-bit MCUs数据手册Microchip规格书

描述 Description

Up to 50 MHz/83 DMIPS, MIPS32® M4K® coreTwo I2S and four SPI modules for Codec and serial communicationsPeripheral Pin Select (PPS) functionalityParallel Master Port (PMP) with dual read/write buffers for graphics interfacesTemperature Range - 40°C to 105°C

特性 Features

• Up to 50 MHz/83 DMIPS, MIPS32® M4K® core
• USB 2.0-compliant Full-speed OTG controller
• Controller Area Network (CAN) 2.0B Compliant with DeviceNetTM addressing support
• Four I2S/SPI modules for Codec and serial communications
• Peripheral Pin Select (PPS) functionality
• Parallel Master Port (PMP) with dual read/write buffers for graphics interfaces
• Temperature Range - 40°C to 105°C
• Operating voltage range of 2.3V to 3.6V
• 512KB Flash memory (plus an additional 3 KB of Boot Flash)
• 64KB SRAM memory
• MIPS16e® mode for up to 40% smaller code size
• Low-power management modes (Sleep and Idle)
• Peripheral Pin Select (PPS) functionality to allow function remap
• Four channels of hardware DMA with automatic data size detection
• Two additional DMA channels dedicated to USB
• Two additional DMA channels dedicated to CAN
• Five UARTs (12.5 Mbps) and two I2C™ modules
• Hardware Real-Time Clock and Calendar (RTCC)
• Five 16-bit and up to two 32-bit Timers/Counters
• Five Capture inputs and Five Compare/PWM outputs
• External graphics interface with up to 34 PMP pins
• Audio data communication: I2S, LJ, RJ, USB
• Audio data control interface: SPI and I2C™
Audio data master clock:
• Generation of fractional clock frequencies
• Can be synchronized with USB clock
• Can be tuned in run-time
• Can be tuned in run-time
ADC Module:
• 10-bit 1 Msps rate with one Sample and Hold (S&H)
• 48 analog inputs
• Can operate during sleep mode
• Flexible and independent ADC trigger sources
Comparators:
• Three dual-input Comparator modules
• Programmable references with 32 voltage points
In-circuit and in-application programming:
• 4-wire MIPS® Enhanced JTAG interface
• Unlimited program and six complex data breakpoints
• IEEE 1149.2-compatible (JTAG) boundary scan