PIC32MX564F064L数据手册Microchip中文资料规格书

特性 Features

• 80MHz/105DMIPS, 32-bit MIPS M4K Core
• USB 2.0 On-The-Go Peripheral with integrated PHY
• CAN2.0b module with 1024 transmit/receive buffers
• 4 Dedicated DMA Channel for USB OTG
• 5 Stage pipeline, Harvard architecture
• MIPS16e mode for up to 40% smaller code size
• Single cycle multiply and hardware divide unit
• 32 x 32-bit Core Registers
• 32 x 32-bit Shadow Registers
• Fast context switch and interrupt response
• 512K Flash (plus 12K boot Flash)
• 64K RAM (can execute from RAM)
• 8 Channel Hardware DMA Controller
• Flash prefetch module with 256 Byte cache
• Lock instructions or data in cache for fast access
• Programmable vector interrupt controller
• Fast and Accurate 16 channel 10-bit ADC,
• Max 1 Mega samples per second at +/- 1LSB, conversion available during SLEEP & IDLE
• RUN, IDLE, and SLEEP modes
• Multiple switchable clock modes for each power mode, enables optimum power settings
• 8 hardware breakpoints (6 Instruction and 2 Data)
• 2 wire programming and debugging interface
• JTAG interface supporting Programming, Debugging and Boundary scan
• iFlow Trace: Non-intrusive Hardware Instruction Trace port (5 Wires)
• Fail-Safe Clock Monitor – allows safe shutdown if clock fails
• Hardware RTCC (Real-Time Clock and Calendar with Alarms)
• 2 Internal oscillators (8MHz & 31KHz)
• Watchdog Timer with separate RC oscillator
• Pin compatible with 16-bit PIC® MCUs
• Serial Communication Modules allow flexible UART/SPI/I2C™ configuration