PI7C9X2G404SLQ中文资料4-Port, 4-Lane, Slimline PCIe Packet Switch数据手册Diodes规格书

描述 Description

The PI7C9X2G404SLQ is an Automotive compliant PCI Express® 2.1 4-port/4-lane PCI Express Switch specifically designed to be AEC-Q100 qualified and meet the latest low-power and lead (Pb)-free requirements. The PI7C9X2G404SLQ is a high-performance, cost-effective solution that can be implemented in systems such as Automotive Safety and Security, Traffic Mapping, Infotainment and Telematics platforms.The PI7C9X2G404SLQ provides one x1 upstream port and three x1 downstream ports. The PI7C9X2G404SLQ provides users the flexibility to expand or fan-out from a wide range of Bridges such as Automotive MCU, FPGA, video processing and other application specification ICs.

特性 Features

Integrated 100MHz Clock Buffer for each downstream port
Reliability, Availability and Serviceability
Supports Data Poisoning and End-to-End CRC
Advanced Error Reporting and Logging
IEEE 1149.1 JTAG interface support
Link Power Management
Supports L0, L0s, L1, L2, L2/L3Ready and L3 link power state
Active state power management for L0s and L1 state
Device State Power Management
Supports D0, D3Hot and D3Cold
3.3V Aux Power support in D3Cold power state
Supports up to 512-byte maximum payload size
Power Dissipation: 650 mW typical in L0 normal mode and 200 mW typical in L1 mode
Automotive Temperature Range: -40°C to 85°C
MTBF: 50,927,360 hours
Package:
128-pin LQFP 14mm x 14mm
Pb free and 100% Green
Enhanced Features: Programmable Driver Current and De-Emphasis Level at each individual port
150ns typical latency for packet running through switch without blocking
 Supports “Cut-through”(Default) as well as “Store and Forward” mode for switching packets
 Advanced Power Savingso    Empty downstream ports are set to idleo    Clock to corresponding circuit is turned off when any port enters L1 or ASPM L1o    Supports Access Control Service (ACS) for peer-to-peer traffico    Supports Address Translation (AT) packet for o    Supports Latency Tolerance Reporting (LTR) to improve Platform Power Managemento    Supports Optimized Buffer Flush Fill (OBFF) to improve Platform Power Management