PI7C9X2G303EL中文资料3-Port, 3-Lane, ExtremeLo PCIe2.0 Packet Switch数据手册Diodes规格书

特性 Features

PCISIG PCI Express 2.1 certificated
Integrated 100MHz Clock buffer for each downstream port
Reliability, Availability and Serviceability
Supports Data Poisoning and End-to-End CRC
Advanced Error Reporting and Logging
IEEE 1149.6 JTAG interface support
Link Power Management
Supports L0, L0s, L1, L2, L2/L3Ready and L3 link power state
Active state power management for L0s and L1 state
Device State Power Management
Supports D0, D3Hot and D3Cold
3.3V Aux Power support in D3Cold power state
Supports up to 512-byte maximum payload size
Power Dissipation: 0.65 W typical in L0 normal mode and 0.2W typical in L1 mode
Industrial Temperature Range: -40° to 85°C
MTBF: 50,927,360 hours
Package: 136-pin aQFN 8mm x 8mm
Pb free and 100% Green
Enhanced FeaturesProgrammable Driver Current and De-Emphasis Level at each individual port
150ns typical latency for packet running through switch without blocking
Supports “Cut-through”(Default) as well as “Store and Forward” mode for switching packets
Advanced Power Savings
Empty downstream ports are set to idle
Clock to corresponding circuit is turned off when any port enters L1 or ASPM L1
Supports Access Control Service (ACS) for peer-to- peer traffic
Supports Address Translation (AT) packet for SR-IOV application
Supports Latency Tolerance Reporting (LTR) to improve Platform Power Management
Supports Optimized Buffer Flush Fill (OBFF) to improve Platform Power Management
ApplicationsWireless AP/ Router
Wire/ Wireless Tele/ data communication Embedded system
Set-top box and consumer devices Industrial control
NAS/ Storage
Printer/ MFP
Peripheral
PCIe Surveillance and Combo cards Notebook internal PCIe fan-out
PC Motherboard PCIe slot expansion