PI6LC4820数据手册集成电路（IC）的应用特定时钟/定时规格书PDF

特性 Features

3.3V supply voltag
Crystal input: 25 MHz
Differential input: 25MHz, 156.25 MHz
Output frequencies of 312.5, 156.25, 125MHz supported
9 LVPECL or LVDS bank selectable outputs
Low 1ps max integrated phase noise design (12kHz to 20MHz)
Optional xtal or clock input selection
PLL Bypass mode for test
Power supply noise rejection: -50 dBc typical @ 156.25 MHz
Packaging (Pb-free & Green): 48-lead 7×7mm TQFN