Phase-Locked Loop Clock Driver with 16 Clock Outputs

Description The PI6C2516 family is a low-skew, low jitter, phase-locked loop (PLL) clock driver, distributing high-frequency clock signals for SDRAM, server and networking applications. By connecting the feedback FB_OUT output to the feedback FB_IN input, the propagation delay from the CLK input

文件：298.63 Kbytes 页数：7 Pages

PERICOMPericom Semiconductor Corporation

百利通百利通半导体

Phase-Locked Loop Clock Driver with 16 Clock Outputs

Diodes

美台半导体

Phase-Locked Loop Clock Driver with 16 Clock Outputs

Description The PI6C2516 family is a low-skew, low jitter, phase-locked loop (PLL) clock driver, distributing high-frequency clock signals for SDRAM, server and networking applications. By connecting the feedback FB_OUT output to the feedback FB_IN input, the propagation delay from the CLK input

文件：298.63 Kbytes 页数：7 Pages

PERICOMPericom Semiconductor Corporation

百利通百利通半导体

Phase-Locked Loop Clock Driver with 16 Clock Outputs

Description\nThe PI6C2516 family is a low-skew, low jitter, phase-locked loop (PLL) clock driver, distributing high-frequency clock signals for SDRAM, server and networking applications. By connecting the feedback FB_OUT output to the feedback FB_IN input, the propagation delay from the CLK input to • High Performance Phase-Locked Loop Clock Distribution for Synchronous DRAM, server and networking applications.\n• Zero Input-to-Output delay: Distribute One Clock Input to four banks of four outputs, with separate output enables for each bank.\n• Allow Clock Input to have Spread Spectrum modulati;

Diodes

美台半导体