PEEL22CV10A中文资料CMOS Programmable Electrically Erasable Logic Device数据手册TI规格书

描述 Description

General Description
The PEEL™22CV10A is a Programmable Electrically Erasable Logic (PEEL™) device providing an attractive alternative to ordinary PLDs. The PEEL™22CV10A offers the performance, flexibility, ease of design and production practicality needed by logic designers today. The PEEL™22CV10A is available in 24-pin DIP, SOIC, TSSOP and 28-pin PLCC packages (see Figure 1), with speeds ranging from 7ns to 25ns and with power consumption as low as 30mA. EE-reprogrammability provides the convenience of instant reprogramming for development and a reusable production inventory, minimizing the impact of programming changes or errors. EE-reprogrammability also improves factory testability, thus ensuring the highest quality possible. The PEEL™22CV10A is JEDEC file compatible with standard 22V10 PLDs. Eight additional configurations per macrocell (a total of 12) are also available by using the “+” software/programming option (i.e., 22CV10A+). The additional macrocell configurations allow more logic to be put into every design. Programming and development support for the PEEL™22CV10A are provided by popular third-party programmers and develop ment software. ICT also offers free PLACE development software.

特性 Features

■ High Speed/Low Power
   - Speeds ranging from 7ns to 25ns
   - Power as low as 30mA at 25MHz■ Electrically Erasable Technology
   - Superior factory testing
   - Reprogrammable in plastic package
   - Reduces retrofit and development costs■ Development/Programmer Support
- Third party software and programmers
- ICT PLACE Development Software■ Architectural Flexibility
   - 132 product term X 44 input AND array
   - Up to 22 inputs and 10 outputs
   - Up to 12 configurations per macrocell
   - Synchronous preset, asynchronous clear
   - Independent output enables
   - 24-pin DIP/SOIC/TSSOP and 28-pin PLCC■ Application Versatility
   - Replaces random logic
   - Pin and JEDEC compatible with 22V10
   - Enhanced Architecture fits more logic than ordinary PLDs