50-150 MHz 1:10 SDRAM clock driver

DESCRIPTION The PCK2510SA is a high-performance, low-skew, low-jitter, phase-locked loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The

文件：78.22 Kbytes 页数：10 Pages

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PCK2510SADH

Overview

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50-150 MHz 1:10 SDRAM clock driver

DESCRIPTION The PCK2510SL is a high-performance, low-skew, low-jitter, phase-locked loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The

文件：78.53 Kbytes 页数：10 Pages

PHI

PHI

50-150 MHz 1:10 SDRAM clock driver

DESCRIPTION The PCK2510SL is a high-performance, low-skew, low-jitter, phase-locked loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The

文件：78.53 Kbytes 页数：10 Pages

PHI

PHI

50-150 MHz 1:10 SDRAM clock driver

DESCRIPTION The PCK2510S is a high-performance, low-skew, low-jitter, phase-locked loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The P

文件：81.51 Kbytes 页数：10 Pages

PHI

PHI