PCA9547D中文资料8-channel I2C-bus multiplexer with reset数据手册恩XP规格书

描述 Description

The PCA9547 is an octal bidirectional translating multiplexer controlled by the I²C-bus. The SCL/SDA upstream pair fans out to eight downstream pairs, or channels. Only one SCx/SDx channel can be selected at a time, determined by the contents of the programmable control register. The device powers up with Channel 0 connected, allowing immediate communication between the master and downstream devices on that channel.
An active LOW reset input allows the PCA9547 to recover from a situation where one of the downstream I²C-buses is stuck in a LOW state. Pulling the RESET pin LOW resets the I²C-bus state machine causing all the channels to be deselected, except Channel 0 so that the master can regain control of the bus.
The pass gates of the multiplexers are constructed such that the VDD pin can be used to limit the maximum high voltage which will be passed by the PCA9547. This allows the use of different bus voltages on each pair, so that 1.8 V, 2.5 V, or 3.3 V parts can communicate with 5 V parts without any additional protection. External pull-up resistors pull the bus up to the desired voltage level for each channel. All I/O pins are 5 V tolerant.

特性 Features

1-of-8 bidirectional translating multiplexer
I²C-bus interface logic; compatible with SMBus standards
Active LOW RESET input
3 address pins allowing up to 8 devices on the I²C-bus
Channel selection via I²C-bus, one channel at a time
Power-up with all channels deselected except Channel 0 which is connected
Low Ron multiplexers
Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and 5 V buses
No glitch on power-up
Supports hot insertion
Low standby current
Operating power supply voltage range of 2.3 V to 5.5 V
5 V tolerant inputs
0 Hz to 400 kHz clock frequency
ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM perJESD22-C101
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
Packages offered: SO24, TSSOP24, HVQFN24