PCA9543AD数据手册集成电路（IC）的专用规格书PDF

描述 Description

The PCA9543A/43B is a bidirectional translating switch, controlled by the I²C-bus. The SCL/SDA upstream pair fans out to two downstream pairs, or channels. Any individual SCx/SDx channels or combination of channels can be selected, determined by the contents of the programmable control register. Two interrupt inputs, INT0 and INT1, one for each of the downstream pairs, are provided. One interrupt output, INT, which acts as an AND of the two interrupt inputs, is provided.
An active LOW reset input allows the PCA9543X to recover from a situation where one of the downstream I²C-buses is stuck in a LOW state. Pulling the RESET pin LOW resets the I²C-bus state machine and causes all the channels to be deselected, as does the internal power-on reset function.
The pass gates of the switches are constructed such that the VDD pin can be used to limit the maximum high voltage which will be passed by the PCA9543X. This allows the use of different bus voltages on each SCx/SDx pair, so that 1.8 V, 2.5 V, or 3.3 V parts can communicate with 5 V parts without any additional protection. External pull-up resistors pull the bus up to the desired voltage level for each channel. All I/O pins are 5 V tolerant.
The PCA9543A and PCA9543B are identical except for the fixed portion of the slave address.

特性 Features

1-of-2 bidirectional translating switches
I²C-bus interface logic; compatible with SMBus standards
2 active LOW interrupt inputs
Active LOW interrupt output
Active LOW reset input
2 address pins allowing up to 4 devices on the I²C-bus
Alternate address versions A and B allow up to a total of 12 devices on the bus for larger systems or to resolve address conflicts
Channel selection via I²C-bus, in any combination
Power-up with all switch channels deselected
Low Ron switches
Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and 5 V buses
No glitch on power-up
Supports hot insertion
Low standby current
Operating power supply voltage range of 2.3 V to 5.5 V
5 V tolerant inputs
0 Hz to 400 kHz clock frequency
ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM perJESD22-C101
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
Packages offered: SO14, TSSOP14