PCA9518DBR集成电路（IC）的专用规格书PDF中文资料

1 Features

1• Expandable Five-Channel Bidirectional Buffer

• 400-kHz Fast I2C Bus

• Operating VCC Range of 3 V to 3.6 V

• 5-V Tolerant I2C and Enable Input Pins to Support

Mixed-Mode Signal Operation

• Active-High Individual Repeater Enable Inputs

• Open-Drain Input/Outputs

• Lockup-Free Operation

• Supports Multiple Masters

• Powered-Off High-Impedance I2C Pins

• I2C Bus and SMBus Compatible

• Latchup Performance Exceeds 100 mA Per JESD

78

• ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

2 Description

The PCA9518 is an expandable five-channel

bidirectional buffer for I2 C and SMBus applications. The I2C protocol requires a maximum bus

capacitance of 400 pF, which is derived from the

number of devices on the I2C bus and the bus length.

The PCA9518 overcomes this restriction by

separating and buffering the I2C data (SDA) and clock (SCL) lines into multiple groups of 400-pF

segments. Any segment-to-segment transition sees

only one repeater delay. Each PCA9518 can

communicate with other PCA9518 hubs through a 4- wire inter-hub expansion bus. Using multiple

PCA9518 parts, any width hub (in multiples of five)

can be implemented using the expansion pins, with

only one repeater delay and no functional

degradation of the system performance.

The PCA9518 does not support clock stretching

across the repeater.