PCA9518APW中文资料恩XP数据手册PDF规格书

General description

The PCA9518A is a CMOS integrated circuit intended for application in I2C-bus and SMBus systems.

While retaining all the operating modes and features of the I2C-bus system, it permits extension of the I2C-bus by buffering both the data (SDA) and the clock (SCL) lines, thus enabling virtually an unlimited number of buses of 400 pF. The I2C-bus capacitance limit of 400 pF restricts the number of devices and bus length.

Using the PCA9518A enables the system designer to divide the bus into an unlimited number of segments off of a hub where any segment to segment transition sees only one repeater delay and is multiple master capable on each segment.

Using multiple PCA9518A parts, any width hub (in multiples of five)1 can be implemented using the expansion pins.

The PCA9518A is a wider voltage range (2.3 V to 3.6 V) version of the PCA9518 and also improves partial power-down performance, keeping I2C-bus I/O pins in high-impedance state when VDD is below 2.0 V.

Features

■ Expandable 5 channel, bidirectional buffer

■ I2C-bus and SMBus compatible

■ Active HIGH individual repeater enable inputs

■ Open-drain input/outputs

■ Lock-up free operation

■ Supports arbitration and clock stretching across the repeater

■ Accommodates Standard-mode and Fast-mode I2C-bus devices and multiple masters

■ Powered-off high-impedance I2C-bus pins

■ Operating supply voltage range of 2.3 V to 3.6 V

■ 5 V tolerant I2C-bus and enable pins

■ 0 Hz to 400 kHz clock frequency2

■ ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101

■ Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA

■ Package offerings: SO20 and TSSOP20