P89LPC931FDH数据手册恩XP中文资料规格书

描述 Description

Overview The P89LPC930/931 are single-chip microcontrollers designed for applications demanding high-integration, low cost solutions over a wide range of performance requirements. The P89LPC930/931 is based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard 80C51 devices. Many system-level functions have been incorporated into the P89LPC930/931 in order to reduce component count, board space, and system cost.

特性 Features

high performance 80C51 CPU provides instruction cycle times of 111 ns to 222 ns for all instructions except multiply and divide when executing at 18 MHz. This is 6 times the performance of the standard 80C51 running at the same clock frequency. A lower clock frequency for the same performance results in power savings and reduced EMI.
2.4 V to 3.6 V VDD operating range. I/O pins are 5 V tolerant (may be pulled up or driven to 5.5 V).
4 kB/8 kB Flash code memory with 1 kB sectors, and 64-byte page size.
Byte-erase allowing code memory to be used for data storage.
Flash program operation completes in 2 ms.
Flash erase operation completes in 2 ms.
256-byte RAM data memory.
Two 16-bit counter/timers. Each timer may be configured to toggle a port output upon timer overflow or to become a PWM output.
Real-Time clock that can also be used as a system timer.
Two analog comparators with selectable inputs and reference source.
Enhanced UART with fractional baud rate generator, break detect, framing error detection, automatic address detection and versatile interrupt capabilities.
400 kHz byte-wide I²C-bus communication port.
SPI communication port.
Eight keypad interrupt inputs, plus two additional external interrupt inputs.
Four interrupt priority levels.
Watchdog timer with separate on-chip oscillator, requiring no external components. The Watchdog time-out time is selectable from 8 values.
Active-LOW reset. On-chip power-on reset allows operation without external reset components. A reset counter and reset glitch suppression circuitry prevent spurious and incomplete resets. A software reset function is also available.
Low voltage reset (Brownout detect) allows a graceful system shutdown when power fails. May optionally be configured as an interrupt.
Oscillator Fail Detect. The watchdog timer has a separate fully on-chip oscillator allowing it to perform an oscillator fail detect function.
Configurable on-chip oscillator with frequency range and RC oscillator options (selected by user programmed Flash configuration bits). The RC oscillator (factory calibrated to +-1 pct) option allows operation without external oscillator components. Oscillator options support frequencies from 20 kHz to the maximum operating frequency of 18 MHz. The RC oscillator option is selectable and fine tunable.
Programmable port output configuration options: Quasi-bidirectional
Open drain
Push-pull
Input-only

Port 'input pattern match'detect. Port 0 may generate an interrupt when the value of the pins match or do not match a programmable pattern.
Second data pointer.
Schmitt trigger port inputs.
LED drive capability (20 mA) on all port pins. Maximum combined I/O current of 100 mA.
Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10 ns minimum ramp times.
23 I/O pins minimum (28-pin package). Up to 26 I/O pins while using on-chip oscillator and reset options.
Only power and ground connections are required to operate the P89LPC930/931 using on-chip oscillator and on-chip reset options.
Serial Flash programming allows in-circuit production coding. Flash security bits prevent reading of sensitive programs.
In-Application Programming of the Flash code memory. This allows changing the code in a running application.
Idle and two different Power-down reduced power modes. Improved wake-up from Power-down mode (a low interrupt input starts execution). Typical Power-down current is 1 uA (total Power-down with voltage comparators disabled).
28-pin TSSOP package.
Emulation support.