P87C591VFA数据手册恩XP中文资料规格书

描述 Description

OverviewThe P8xC591 is a single-chip 8-bit-high-performance microcontroller, with on-chip CAN-controller, derived from the 80C51 microcontroller family.
It uses the powerful 80C51 instruction set and includes the successful PeliCAN functionality of the SJA1000 CAN controller from Philips Semiconductors.
The fully static core provides extended power save provisions as the oscillator can be stopped and easily restarted without loss of data. The improved internal clock prescaler of 1:1 achieves a 500 ns instruction cycle time at 12 MHz external clock rate.
The microcontroller is manufactured in an advanced CMOS process, and is designed for use in automotive and general industrial applications. In addition to the 80C51 standard features, the device provides a number of dedicated hardware functions for these applications.
Two versions of the P8xC591 will be offered:
P83C591 (with ROM)
P87C591 (with OTP)
Hereafter these versions will be referred to as P8xC591. The temperature range includes (max. fCLK= 12 MHz):
-40 to +85 Cel version, for general applications The P8xC591 combines the functions of the P87C554 (microcontroller) and the SJA1000 (stand-alone CAN-controller) with the following enhanced features:
Enhanced CAN receive interrupt (level sensitive)
Extended acceptance filter
Acceptance filter changeable \"on the fly\".
The main differences between P8xC591 and P87C554 are:
CAN-controller on chip
6-input ADC
Low active Reset
44 leads.

特性 Features

80C51 Related of the 8xC591



•Full static 80C51 Central Processing Unit available as OTP, ROM and ROMless

•16 Kbytes internal Program Memory expandable externally to 64 Kbytes

•512 bytes on-chip Data RAM expandable externally to 64 Kbytes

•Three 16-bit timers/counters T0, T1 (standard 80C51) and additional T2 (capture & compare)

•10-bit ADC with 6 multiplexed analog inputs with fast 8-bit ADC option

•Two 8-bit resolution, Pulse Width Modulated outputs

•32 I/O port pins in the standard 80C51 pinout

•I²C-bus serial I/O port with byte oriented master and slave functions

•On-chip Watchdog Timer T3

•Extended temperature range: -40 to +85 Cel

•Accelerated (prescaler 1:1) instruction cycle time 500 ns @ 12 MHz

•Operation voltage range: 5 V +- 5 pct

•Security bits:
•ROM version has 2 bits

•OTP/EPROM version has 3 bits




•32 bytes Encryption array

•4 level priority interrupt, 15 interrupt sources

•Full-duplex enhanced UART with programmable Baudrate Generator

•Power Control Modes:
•Clock can be stopped and resumed

•Idle Mode

•Power-down Mode




•ADC active in Idle Mode

•Second DPTR register

•ALE inhibit for EMI reduction

•Programmable I/O port pins (pseudo bi-directional, push-pull, high impedance, open drain)

•Wake-up from Power-down by external interrupts

•Software reset bit (AUXR1.5)

•Low active reset pin

•Power-on detect reset

•Once mode



CAN Related of the 8xC591



•CAN 2.0B active controller, supporting 11-bit Standard and 29-bit Extended indentifiers

•1 Mbit/s CAN bus speed with 8 MHz clock achievable

•64 byte receive FIFO (can capture sequential Data Frames from the same source as required by the Transport Layer of higher protocols such as DeviceNet, CANopen and OSEK)

•13 byte transmit buffer

•Enhanced PeliCAN core (from the SJA1000 stand-alone CAN2.0B controller)



PELICAN FEATURES



•Four independently configurable Screeners (Acceptance Filters)

•Each Screener has two 32-bit specifies:
•32-bit Match and

•32-bit Mask




•32-bits of Mask per Screener allows unique Group addressing per Screener


•Higher layer protocols especially supported in Standard CAN format with:
•Up to four, 11-bit ID Screeners that also Screen the two (2) Data Bytes

•i.e., Data Frames are Screened by the CAN ID and by Data Byte content




•Up to eight, 11-bit ID Screeners half of which also Screen the first Data Byte

•All Screeners are changeable \"on the fly\"

•Listen Only Mode, Self Test Mode

•Error Code Capture, Arbitration Lost Capture, readable Error Counters



Errata Sheet

应用 Application

Relay driver

High speed line driver

Logic level translator.