P60C080PX81中文资料恩XP数据手册PDF规格书

Introduction

The new NXP Semiconductors SmartMX2 P60 family was created in order to cover all

important market requests for state-of-the-art security chip controllers:

• Innovative and unique security measures, Common Criteria certified

• Superior transaction and personalization time

• Broadest portfolio of memory configurations with contact, dual-interface and

contactless on a single platform

• Proven SmartMX reliability, interoperability and RF excellence for shortest

time-to-market

• Market benchmark in view of cost-performance ratio

Further feature improvements in comparison to the existing approved SmartMX P5 family:

• Significant increases in controller and crypto performance

• Further extended CPU instructions for Java and C code

• Comprehensive hardware support for efficient and secure OS implementation

• Highest transaction and personalization speed

• Excellent power efficiency

• New-generation Fame2 crypto coprocessor for RSA/ECC

• New-generation Symmetric Block Cipher (SBC) crypto coprocessor for DES/AES

• Advanced 90 nm CMOS technology

Other important SmartMX2 P60 differentiators in the market are:

• New development tool suite, totally revised and based on an optimized

close-to-product true bond-out chip emulation approach

• Broadest portfolio of certified package variations

General description

The P60C080 and P60C144 devices are members of the new SmartMX2 Family and offer

with their two different EEPROM size variations a common set of functional blocks and

interfaces, supporting high-performance, high-security contact applications. Figure 1

shows the block diagram of the modular controller architecture consisting of the following

blocks and features:

• SmartMX2 CPU with enhanced application instruction set supporting 32-/24-/16-/8-bit

move, logical and arithmetic functions

• Fame2 coprocessor based on innovative power-efficient and fast architecture for

optimized RSA/ECC cryptography

• SBC coprocessor interface with multiple data/key register sets now supporting both

AES and Triple-DES

• ISO/IEC 7816 data transfer improved with enhanced protocol support for T=0 and

T=1 protocols

• New Copy Machines supporting direct memory access (DMA) to memories and all

SFRs

• Cyclic Redundancy Check (CRC) coprocessors 16-bit/32-bit

• Memory Management Unit (MMU) with 16 cache segments

• New security features especially targeting combined laser light attacks and integrity of

code execution and data fetch

• Development tool suite based on approved suppliers Keil and Ashling

– μVision4 user interface

– New and high-performance emulation hardware “SmartICE series”

• High-memory SoftMasking device for code development purposes

• Common Criteria security certified high-performance crypto library supporting various

algorithms

• Consequent family concept with regard to all future platforms of the P60 family