Integrated Circuit Low-Noise JFET-Input Operational Amplifier

Description: The NTE857M and NTE857SM are low–noise JFET input operational amplifiers combining two state–of–the–art linear technologies on a single monolithic integrated circuit. Each internally compensated operational amplifier has well matched high voltage JFET input devices for low input of

文件：28.14 Kbytes 页数：3 Pages

NTE

66-150MHz Phase Locked Loop Differential 1:10 SDRAM Clock Driver

DESCRIPTION Zero delay buffer to distribute an SSTL differential clock input pair to 10 SSTL_2 differential output pairs. Outputs are slope controlled. External feedback pin for synchronization of the outputs to the input. A CMOS style Enable/Disable pin is provided for low power disable. FEAT

文件：62.58 Kbytes 页数：8 Pages

PHI

PHI

66-150MHz Phase Locked Loop Differential 1:10 SDRAM Clock Driver

DESCRIPTION Zero delay buffer to distribute an SSTL differential clock input pair to 10 SSTL_2 differential output pairs. Outputs are slope controlled. External feedback pin for synchronization of the outputs to the input. A CMOS style Enable/Disable pin is provided for low power disable. FEAT

文件：62.58 Kbytes 页数：8 Pages

PHI

PHI

70-190 MHz differential 1:10 clock driver

文件：84.67 Kbytes 页数：12 Pages

PHI

PHI