NT5DS32M8CS-5T中文资料NANOAMP数据手册PDF规格书

Description

NT5DS64M4CT, NT5DS32M8CT and NT5DS16M16CT, NT5DS64M4CS, NT5DS32M8CS and NT5DS16M16CS are 256Mb SDRAM devices based using a DDR interface. They are all based on Nanya’s 110 nm design process.

The 256Mb DDR SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 256Mb DDR SDRAM effectively consists of a single 2n-bit wide, one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.

Features

• DDR 256M bit, die C, based on 110nm design rules

• Double data rate architecture: two data transfers per clock cycle

• Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver

• DQS is edge-aligned with data for reads and is center aligned with data for writes

• Differential clock inputs (CK and CK)

• Four internal banks for concurrent operation

• Data mask (DM) for write data

• DLL aligns DQ and DQS transitions with CK transitions

• Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS

• Burst lengths: 2, 4, or 8

• CAS Latency: 2/2.5(DDR333), 2.5/3(DDR400)

• Auto Precharge option for each burst access

• Auto Refresh and Self Refresh Modes

• 7.8µs Maximum Average Periodic Refresh Interval

• 2.5V (SSTL_2 compatible) I/O

• VDD = VDDQ = 2.5V ± 0.2V (DDR333)

• VDD = VDDQ = 2.6V ± 0.1V (DDR400)

• Available in Halogen and Lead Free packaging