128Mb Double Data Rate SDRAM

• Double data rate architecture: two data transfers per clock cycle • Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver • DQS is edge-aligned with data for reads and is centeraligned with data for writes • Differential clock

文件：3.32175 Mbytes 页数：76 Pages

Nanya

南亚科

128Mb Double Data Rate SDRAM

• Double data rate architecture: two data transfers per clock cycle • Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver • DQS is edge-aligned with data for reads and is centeraligned with data for writes • Differential clock

文件：3.32175 Mbytes 页数：76 Pages

Nanya

南亚科

128Mb Double Data Rate SDRAM

• Double data rate architecture: two data transfers per clock cycle • Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver • DQS is edge-aligned with data for reads and is centeraligned with data for writes • Differential clock

文件：3.32175 Mbytes 页数：76 Pages

Nanya

南亚科

128Mb Double Data Rate SDRAM

• Double data rate architecture: two data transfers per clock cycle • Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver • DQS is edge-aligned with data for reads and is centeraligned with data for writes • Differential clock

文件：3.32175 Mbytes 页数：76 Pages

Nanya

南亚科