NB7VQ1006M数据手册集成电路（IC）的专用逻辑器件规格书PDF

描述 Description

The NB7VQ1006M is a high performance EQualizer Receiver (signal enhancer) that operates up to 10 Gbps/7.5 GHz with a 1.8 V or 2.5 V power supply. When placed in series with a Data/Clock path, it will enhance the degraded signal transmitted across a FR4 backplane or cable interconnect and output six identical CML copies of the input signal. The EQualizer ENable pin (EQEN) allows the IN/IN inputs to either flow through or bypass the EQualizer section. Control of the EQualizer function is realized by setting EQEN. When EQEN is set Low, the IN / IN inputs bypass the Equalizer. When EQEN is set High, the IN / IN inputs flow through the EQualizer. The default state at start-up is LOW. The differential Data/Clock inputs incorporate a pair of internal 50-ohm termination resistors, in a 100-ohm center-tapped configuration, via the VT Pin and will accept differential LVPECL, CML or LVDS logic levels. This feature provides transmission line termination on-chip, at the receiver end, eliminating external components. The NB7VQ1006M is a member of the PEEQ GigaComm™ family of high performance Data/Clock products.

特性 Features

• Maximum Input Data Rate > 10 Gbps
• Higher Data rate
• Maximum Input Clock Frequency > 7.5 GHz
• Higher Data rate
• Backplane and Cable Interconnect Compensation
• Longer trace runs
• Differential CML Outputs, 400 mV Peak-to-Peak, Typical
• Design Flexibility
• Operating Range: VCC = 1.71 V to 2.625 V, GND = 0 V
• Design Flexibility
• -40°C to +85°C Ambient Operating Temperature
• Design Flexibility

应用 Application

• Backplane and Cable Interconnect Compensation

简介

NB7VQ1006M属于集成电路（IC）的专用逻辑器件。由制造生产的NB7VQ1006M专用逻辑器件专用逻辑 IC 设计提供应用特定的逻辑输出类型，例如 BCD 速率倍增、可寻址扫描端口、总线终端阵列、CML 驱动器、比较器、ABT 扫描测试、二进制全加法器、互补对加逆变器、可配置缓冲器、触点颤动消除器、晶体振荡器、延迟元件、差分接收器、LVTTL 到 GTLP 收发器、存储器解码器、电源良好检测器和分频器。