2.5V/3.3V 12 Gb/s Differential Clock/Data SmartGate with CML Output and Internal Termination

文件：1.72782 Mbytes 页数：12 Pages

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2.5V/3.3V 12 Gb/s Differential Clock/Data SmartGate with CML Output and Internal Termination

文件：1.42261 Mbytes 页数：12 Pages

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2.5V/3.3V 12 Gb/s Differential Clock/Data SmartGate with CML Output and Internal Termination

文件：1.42261 Mbytes 页数：12 Pages

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2.5V/3.3V 12 Gb/s Differential Clock/Data SmartGate with CML Output and Internal Termination

文件：1.72782 Mbytes 页数：12 Pages

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2.5V/3.3V 12 Gb/s Differential Clock/Data SmartGate with CML Output and Internal Termination

文件：1.42261 Mbytes 页数：12 Pages

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2.5V/3.3V 12 Gb/s Differential Clock/Data SmartGate with CML Output and Internal Termination

文件：1.72782 Mbytes 页数：12 Pages

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2.5V/3.3V 12 Gb/s Differential Clock/Data SmartGate with CML Output and Internal Termination

文件：1.72782 Mbytes 页数：12 Pages

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2.5V/3.3V 12 Gb/s Differential Clock/Data SmartGate with CML Output and Internal Termination

文件：1.72782 Mbytes 页数：12 Pages

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2.5V/3.3V 12 Gb/s Differential Clock/Data SmartGate with CML Output and Internal Termination

文件：1.42261 Mbytes 页数：12 Pages

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2.5 V / 3.3 V, 12 Gb/s Differential Clock / Data Smart Gate with CML Output and Internal Termination

The NB7L86M is a multi-function differential Logic Gate, whichcan be configured as an AND/NAND, OR/NOR, XOR/XNOR, or 2:1MUX. This device is part of the GigaComm family of highperformance Silicon Germanium products. The NB7L86M is anultra-low jitter multi-logic gate with a maximum data rate of 12 Gb/ • Maximum Input Clock Frequency up to 8 GHz\n• 30 ps Typical Rise and Fall Times\n• 2 ps Typical Within Device Skew\n• CML Output with Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V\n• 50 Ω Internal Input and Output Termination Resistors\n• Pb-Free Packages are Available;

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