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N74F50729N中文资料PDF规格书
N74F50729N规格书详情
DESCRIPTION
The 74F50729 is a dual positive edge–triggered D–type featuring individual data, clock, set and reset inputs; also true and complementary outputs.
The 74F50729 is designed so that the outputs can never display a metastable state due to setup and hold time violations. If setup time and hold time are violated the propagation delays may be extended beyond the specifications but the outputs will not glitch or display a metastable state. Typical metastability parameters for the 74F50729 are: τ ≅ 135ps and τ ≅ 9.8 X 106 sec where τ represents a function of the rate at which a latch in a metastable state resolves that condition and To represents a function of the measurement of the propensity of a latch to enter a metastable state.
FEATURES
• Metastable immune characteristics
• Output skew less than 1.5ns
• High source current (IOH = 15mA) ideal for clock driver applications
• See 74F5074 for synchronizing dual D–type flip–flop
• See 74F50109 for synchronizing dual J–K positive edge–triggered flip–flop
• See 74F50728 for synchronizing cascaded dual D–type flip–flop
• Industrial temperature range available (–40°C to +85°C)
供应商 | 型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
---|---|---|---|---|---|---|---|
NXP |
1815+ |
SOP14-3.9 |
6528 |
只做原装正品现货!或订货,假一赔十! |
询价 | ||
ROHS |
SMD |
56520 |
一级代理 原装正品假一罚十价格优势长期供货 |
询价 | |||
PHILIPS/飞利浦 |
1535+ |
30473 |
询价 | ||||
NXP |
22+ |
14SOIC |
9000 |
原厂渠道,现货配单 |
询价 | ||
PHI |
23+ |
SOP |
8890 |
价格优势/原装现货/客户至上/欢迎广大客户来电查询 |
询价 | ||
PHI |
6000 |
面议 |
19 |
SOP |
询价 | ||
PHILIPS/飞利浦 |
22+ |
SOIC-14 |
9600 |
原装现货,优势供应,支持实单! |
询价 | ||
PHI |
22+ |
SOIC-143.9mm |
360000 |
进口原装房间现货实库实数 |
询价 | ||
PHILIPS |
21+ |
SOIC-14 |
10000 |
原装现货假一罚十 |
询价 | ||
PHILIPS/飞利浦 |
2021+ |
SOP14 |
100500 |
一级代理专营品牌!原装正品,优势现货,长期排单到货 |
询价 |