N74F2373N中文资料飞利浦数据手册PDF规格书

DESCRIPTION

The 74F2373 is an octal transparent latch coupled to eight 3-State output devices. The two sections of the device are controlled independently by enable (E) and output enable (OE) control gates.

The 30 Ohm series termination on the outputs reduces over/undershoot, making them ideal for driving DRAM The data on the D inputs is transferred to the latch outputs when the enable (E) input is high. The latch remains transparent to the data input while E is high, and stores the data that is present one setup time before the high-to-low enable transition.

The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors.

FEATURES

• 8-bit transparent latch

• 30 Ohm output termination for driving DRAM

• 3-State outputs glitch free during power-up and power-down

• Common 3-State output register

• Independent register and 3-State buffer operation