N74F225N中文资料飞利浦数据手册PDF规格书

DESCRIPTION

This 80–bit active element First–In–First–Out (FIFO) is a monolithic Schottky–clamped transistor–transistor logic (STTL) array organized as 16–words of 5–bits each. A memory system using the ’F225 can be easily expanded in multiples of 16–words of 5–bits as shown in Figure 1. The 3–State outputs controlled by a single enable input (OE) make bus connection and multiplexing simple. The ’F225 processes data in a parallel format at any desired clock rate from DC to 25MHz.

FEATURES

• Independent synchronous inputs and outputs

• Organized as 16 words of 5 bits

• DC to 25MHz data rate

• 3–State outputs

• Cascadable in word–width and depth direction