16X5 asynchronous FIFO 3-State

DESCRIPTION This 80–bit active element First–In–First–Out (FIFO) is a monolithic Schottky–clamped transistor–transistor logic (STTL) array organized as 16–words of 5–bits each. A memory system using the ’F225 can be easily expanded in multiples of 16–words of 5–bits as shown in Figure 1. The 3–

文件：122.16 Kbytes 页数：14 Pages

PHI

PHI

16X5 asynchronous FIFO (3-State)

DESCRIPTION\nThis 80–bit active element First–In–First–Out (FIFO) is a monolithic Schottky–clamped transistor–transistor logic (STTL) array organized as 16–words of 5–bits each. A memory system using the ’F225 can be easily expanded in multiples of 16–words of 5–bits as shown in Figure 1. The 3–Stat • Independent synchronous inputs and outputs\n• Organized as 16 words of 5 bits\n• DC to 25MHz data rate\n• 3–State outputs\n• Cascadable in word–width and depth direction ;

恩XP

16X5 asynchronous FIFO 3-State

DESCRIPTION This 80–bit active element First–In–First–Out (FIFO) is a monolithic Schottky–clamped transistor–transistor logic (STTL) array organized as 16–words of 5–bits each. A memory system using the ’F225 can be easily expanded in multiples of 16–words of 5–bits as shown in Figure 1. The 3–

文件：122.16 Kbytes 页数：14 Pages

PHI

PHI

16X5 asynchronous FIFO 3-State

DESCRIPTION This 80–bit active element First–In–First–Out (FIFO) is a monolithic Schottky–clamped transistor–transistor logic (STTL) array organized as 16–words of 5–bits each. A memory system using the ’F225 can be easily expanded in multiples of 16–words of 5–bits as shown in Figure 1. The 3–

文件：122.16 Kbytes 页数：14 Pages

PHI

PHI

High Q, high self-resonant frequency Varnish coated

文件：429.04 Kbytes 页数：1 Pages

BOURNS

伯恩斯