MT4LC4M16F5中文资料美光数据手册PDF规格书

GENERAL DESCRIPTION

The 4 Meg x 16 DRAM is a high-speed CMOS, dynamic random-access memory device containing 67,108,864 bits organized in a x16 configuration. The MT4LC4M16F5 is functionally organized as 4,194,304 locations containing 16 bits each. The 4,194,304 memory locations are arranged in 4,096 rows by 1,024 columns. During READ or WRITE cycles, each location is uniquely addressed via the address bits: 12 row address bits (A0-A11) and 10 column-address bits (A0-A9). In addition, both byte and word accesses are supported via the two CAS# pins (CASL# and CASH#). The CAS# functionality and timing related to address and control functions (e.g., latching column addresses or selecting CBR REFRESH) are such that the internal CAS# signal is determined by the first external CAS# signal (CASL# or CASH#) to transition LOW and the last to transition back HIGH. The CAS# functionality and timing related to driving or latching data are such that each CAS# signal independently controls the associ ated eight DQ pins.

The row address is latched by the RAS# signal, then the column address by CAS#. The device provides FAST PAGE-MODE operation, allowing for fast successive data operations (READ, WRITE, or READ-MODIFY WRITE) within a given row.

The MT4LC4M16F5 must be refreshed periodically in order to retain stored data.

FEATURES

• Single +3.3V ±0.3V power supply

• Industry-standard x16 pinout, timing, functions, and packages

• 12 row, 10 column addresses

• High-performance CMOS silicon-gate process

• All inputs, outputs and clocks are LVTTL-compatible

• FAST PAGE MODE (FPM) access

• 4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH distributed across 64ms