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MT48LC8M16A2FC-7EIT中文资料镁光数据手册PDF规格书
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MT48LC8M16A2FC-7EIT规格书详情
General Description
The 128Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 134,217,728 bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x4’s 33,554,432-bit banks is organized as 4096 rows by 2048 columns by 4 bits. Each of the x8’s 33,554,432-bit banks is organized as 4096 rows by 1024 columns by 8 bits. Each of the x16’s 33,554,432-bit banks is organized as 4096 rows by 512 columns by 16 bits.
Read and write accesses to the SDRAM are burst-oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA[1:0] select the bank; A[11:0] select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access.
The 128Mb SDRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high speed, fully random access. Precharging one bank while accessing one of the other three banks will hide the PRECHARGE cycles and provide seamless, high-speed, random-access operation.
The 128Mb SDRAM is designed to operate in 3.3V memory systems. An auto refresh mode is provided, along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible.
The devices offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time, and the capability to randomly change column addresses on each clock cycle during a burst access.
Features
• PC100- and PC133-compliant
• Fully synchronous; all signals registered on positive edge of system clock
• Internal, pipelined operation; column address can be changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths (BL): 1, 2, 4, 8, or full page
• Auto precharge, includes concurrent auto precharge and auto refresh modes
• Auto refresh mode; standard and low power
– 64ms, 4096-cycle (industrial)
– 16ms, 4096-cycle refresh (automotive)
• LVTTL-compatible inputs and outputs
• Single 3.3V ±0.3V power supply
• AEC-Q100
• PPAP submission
• 8D response time
产品属性
- 型号:
MT48LC8M16A2FC-7EIT
- 制造商:
MICRON
- 制造商全称:
Micron Technology
- 功能描述:
SYNCHRONOUS DRAM
供应商 | 型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
---|---|---|---|---|---|---|---|
MICRON |
2017+ |
TSOP |
6528 |
只做原装正品!假一赔十! |
询价 | ||
23+ |
TSOP54 |
20000 |
原厂原装正品现货 |
询价 | |||
MICRON |
21+ |
FBGA |
35200 |
一级代理/放心采购 |
询价 | ||
MICRON |
TSOP |
68900 |
原包原标签100%进口原装常备现货! |
询价 | |||
MICRON |
21+ |
BGA/TSOP |
50000 |
特价来袭!美光一级代理入驻114电子网 |
询价 | ||
MICRON |
2022 |
TSOP54 |
120 |
原厂原装正品,价格超越代理 |
询价 | ||
MICRON |
19+ |
TSOP |
256800 |
原厂代理渠道,每一颗芯片都可追溯原厂; |
询价 | ||
MICRON/美光 |
22+ |
TSOP |
19800 |
原装正品 |
询价 | ||
MICRON |
17+ |
TSOP |
6200 |
100%原装正品现货 |
询价 | ||
MICRON |
21+ |
TSOP54 |
56000 |
公司进口原装现货 批量特价支持 |
询价 |