MPC9993DFA中文资料摩托罗拉数据手册PDF规格书

Intelligent Dynamic Clock Switch (IDCS) PLL Clock Driver

The MPC9993 is a PLL clock driver designed specifically for redundant clock tree designs. The device receives two differential LVPECL clock signals from which it generates 5 new differential LVPECL clock outputs. Two of the output pairs regenerate the input signals frequency and phase while the other three pairs generate 2x, phase aligned clock outputs.

Features:

• Fully Integrated PLL

• Intelligent Dynamic Clock Switch

• LVPECL Clock Outputs

• LVCMOS Control I/O

• 3.3V Operation

• 32–Lead LQFP Packaging