MPC9992中文资料摩托罗拉数据手册PDF规格书

3.3V Differential ECL/PECL PLL Clock Generator

The MPC9992 is a 3.3 V compatible, PLL based PECL clock driver. Using SiGe technology and a fully differential design ensures optimum skew and PLL jitter performance. The performance of the MPC9992 makes the device ideal for workstation, mainframe computer and telecommunication applications. With output frequencies up to 400 MHz and output skews less than 150 ps1 the device meets the needs of the most demanding clock applications. The MPC9992 offers a differential PECL input and a crystal oscillator interface. All control signals are LVCMOS compatible.

特性 Features

• 7 differential outputs, PLL based clock generator

• SiGe technology supports minimum output skew (max. 150 ps1)

• Supports up to two generated output clock frequencies with a maximum clock frequency up to 400 MHz

• Selectable crystal oscillator interface and PECL compatible clock input

• SYNC pulse generation

• PECL compatible differential clock inputs and outputs

• Single 3.3V (PECL) supply

• Ambient temperature range 0°C to +70°C

• Standard 32 lead LQFP package

• Pin and function compatible to the MPC992