MPC950中文资料摩托罗拉数据手册PDF规格书

Low Voltage PLL Clock Driver

The MPC950/951 are 3.3V compatible, PLL based clock driver devices targeted for high performance clock tree designs. With output frequencies of up to 180MHz and output skews of 375ps the MPC950 is ideal for the most demanding clock tree designs. The devices employ a fully differential PLL design to minimize cycle–to–cycle and long term jitter. This parameter is of significant importance when the clock driver is providing the reference clock for PLL’s on board today’s microprocessors and ASiC’s. The devices offer 9 low skew outputs, the outputs are configurable to support the clocking needs of the various high performance microprocessors.

• Fully Integrated PLL

• Oscillator or Crystal Reference Input

• Output Frequency up to 180MHz

• Outputs Disable in High Impedance

• Compatible with PowerPC™, Intel and High Performance RISC Microprocessors

• TQFP Packaging

• Output Frequency Configurable

• ±100ps Typical Cycle–to–Cycle Jitter