MPC949中文资料摩托罗拉数据手册PDF规格书

Low Voltage 1:15 PECL to CMOS Clock Driver

The MPC949 is a low voltage CMOS, 15 output clock buffer. The 15 outputs can be configured into a standard fanout buffer or into 1X and 1/2X combinations. The device features a low voltage PECL input, in addition to its LVCMOS/LVTTL inputs, to allow it to be incorporated into larger clock trees which utilize low skew PECL devices (see the MC100LVE111 data sheet) in the lower branches of the tree. The fifteen outputs were designed and optimized to drive 50Ω series or parallel terminated transmission lines. With output to output skews of 300ps the MPC949 is an ideal clock distribution chip for synchronous systems which need a tight level of skew from a large number of outputs. For a similar product with a smaller fanout and package consult the MPC946 data sheet.

• Clock Distribution for Pentium™ Systems with PCI

• Low Voltage PECL Clock Input

• 2 Selectable LVCMOS/LVTTL Clock Inputs

• 350ps Maximum Output to Output Skew

• Drives up to 30 Independent Clock Lines

• Maximum Output Frequency of 150MHz

• High Impedance Output Enable

• 52–Lead TQFP Packaging

• 3.3V VCC Supply