MPC859TCZP100A中文资料PowerQUICC, 32 Bit Power Architecture, 100MHz, Communications Processor, -40 to 100C数据手册恩XP规格书

描述 Description

The MPC859T Quad Integrated Communications Controller (PowerQUICC™) is a versatile one-chip integrated microprocessor and peripheral combination that can be used in a variety of controller applications. It particularly excels in both communications and networking systems.
The MPC859T is a Power Architecture-based derivative of NXP® Semiconductors's MC68360 Quad Integrated Communications Controller (QUICC™). The embedded CPU on the MPC859T is a 32-bit processor (the MPC8xx core) built on Power Architecture technology that incorporates memory management units (MMUs) and instruction and data caches. The communications processor module (CPM) from the MC68360 QUICC has been enhanced by the addition of the inter-integrated controller (I2C) channel. The memory controller has been enhanced, enabling the MPC859T to support any type of memory, including high-performance memories and new types of DRAMs. A PCMCIA socket controller supports up to two sockets. A real-time clock has also been integrated.

特性 Features

The following list summarizes the key MPC859T features:
• Embedded MPC8xx core
• Single-issue, 32-bit version of the core (compatible with the Power Architecturedefinition) with 32, 32-bit general-purpose registers (GPRs)
• The MPC859T provides enhanced ATM functionality over that of the MPC860SAR.The MPC859T adds major new features available in \"enhanced SAR\" (ESAR) mode,including the following:
• Multiple APC priority levels available to support a range of trafficpace requirements
• Port-to-port switching capability without the need for RAM-based microcode
• Simultaneous MII (100Base-T) and UTOPIA (half-duplex) capability
• Parameter RAM for both SPI and I2C can be relocated withoutRAM-based microcode
• Supports full-duplex UTOPIA master (ATM side) operation using a \"split\" bus
• Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)
• 32 address lines
• Complete static design
• Memory controller (eight banks)
• General-purpose timers
• Fast Ethernet controller (FEC)
• System integration unit (SIU)
• Interrupts
• Communications processor module (CPM)
• On-chip 16 x 16 multiply accumulate controller (MAC)
• Four baud rate generators
• One SCC (serial communication controller)
• Two SMCs (serial management channels)
• One SPI (serial peripheral interface)
• One I2C (inter-integrated circuit) port
• Time-slot assigner (TSA)
• Parallel interface port (PIP)
• PCMCIA interface
• Low power support
• Debug interface
• 3.3 V operation
• 357-pin PBGA package

应用 Application

Secure Transaction and Retail Payments
•POS Printer