MPC8572VJAULE数据手册恩XP中文资料规格书

描述 Description

NXP’s next-generation PowerQUICC® III integrated communications processors are designed to provide solutions for symmetrical and asymmetrical multi-core systems. Based on the scalable e500 processor and system-on-chip (SoC) platform, they deliver dual-core gigahertz plus processing performance with advanced content processing and security features.
The MPC8572E family of processors offers clock speeds from 1.2 GHz up to 1.5 GHz, combining two powerful e500 processor cores built on Power Architecture® technology, enhanced peripherals and high-speed interconnect technology to balance processor performance with I/O system throughput. These processors also contain application acceleration blocks such as a table lookup unit (TLU) that offloads complex table searches and header inspections, a pattern-matching engine to handle regular expression matching with a deflate engine to manage file decompression and a security engine that accelerates crypto operations in IPsec and SSL/TLS for VPNs.
Based on NXP®.s 90 nm silicon-on-insulator (SOI) copper interconnect process technology, the MPC8572E is designed to deliver higher performance with lower power dissipation. The MPC8572E processors provide a significant performance increase and represent continuous innovation from the popular PowerQUICC family. With uncompromising integration, the MPC8572E platform builds on the embedded core performance of Power Architecture technology and adds new features to enhance traffic management and security acceleration.
Support for high-speed interfaces on the MPC8572E enables scalable connectivity to network processors and/or ASICs in the data plane while the MPC8572E platform handles complex, computationally demanding control plane processing tasks. These processors include dual memory controllers supporting DDR2 and DDR3 for future proofing and error correction codes for high reliability, enhanced Gigabit Ethernet (GbE) support and double precision floating point.

特性 Features

• Dual e500 Power Architecture cores scaling to 1.5 GHz
• 1 MB L2 cache/SRAM with I/O stashing
• 32 KB I/D L1 cache per core
• Dual integrated DDR2/DDR3 SDRAM memory controllers
• 64-bits (72-bits with ECC) per controller
• to 800 MHz datarate
• Four integrated Ethernet controllers (enhanced TSEC)
• 10/100/1000 support
• TCP/UPD offload
• Quality of service support
• IEEE® 1588 support
• Lossless flow control
• SGMII interfaces
• Single 10/100 fast Ethernet controller (FEC) with MII (muxed)
• TLU offloading complex table searches
• Pattern matching engine searches for regular expressions within packet payloads
• Includes packet deflate engine to expose zipped payloads
• Security engine
• DES, 3DES, MD-5, SHA-1/2, AES, RSA, RNG, Kasumi F8/F9 and ARC-4 encryption algorithms
• PCI Express®
• Serial RapidIO®
• 32-bit local bus running up to 133 MHz
• Dual I²C, Dual DMA, DUART, multiprocessor interrupt controller, IEEE1149.1 JTAG test access port
• 1023-pin FC-PBGA package
• This product is included in NXP®.s product longevity program, with assured supply for a minimum of 10 years after launch

应用 Application

Secure Transaction and Retail Payments
•POS Printer