MPC566

NEXUS Debugger and Trace for PowerPC

MPC566

RISC MCU with Code Compression Option

MPC5668E

MPC5668x Microcontroller

MPC5668xfeatures: •32-bitCPUcorecomplex(e200z650) –CompliantwithPowerArchitectureembeddedcategory –32KBunifiedcachewithlinelockingandeight-entry storebuffer16 –Executionspeedstaticto116MHz •32-bitI/Oprocessor(e200z0) –Executionspeedstaticto1/2CPUcores

ETC

MPC5668G

MPC5668x Microcontroller

MPC5668xfeatures: •32-bitCPUcorecomplex(e200z650) –CompliantwithPowerArchitectureembeddedcategory –32KBunifiedcachewithlinelockingandeight-entry storebuffer16 –Executionspeedstaticto116MHz •32-bitI/Oprocessor(e200z0) –Executionspeedstaticto1/2CPUcores

ETC

MPC5668G

超可靠的MPC5668G MCU，适用于汽车和工业安全应用; 支持目前所有的汽车通信协议\n针对通信数据管理进行了优化： 592 KB嵌入式RAM，被分成两个分块，支持多个总线主设备同时存取。\n另有e200z0内核对来自高速网络(如FlexRayTM和以太网)的通信数据进行预处理。\n\n单芯片SoC\n 本产品包含在恩智浦产品长期供货计划中，自推出后至少保证15年供货\n超高可靠性MCU\n;

恩智浦MPC5668G MCU双核处理器适合汽车网关应用，能够通过单一节点连接汽车上所有可能存在的通信协议。 \n提供了所需要的吞吐性能，保证实时运行\n单芯片SoC解决方案提供最佳成本效益和EMC性能\n支持目前所有的汽车通信协议\n还有强大的第三方生态系统的工具和软件作为后盾，支持开发\n

恩XP

MPC5668X

MPC5668x Microcontroller

MPC5668xfeatures: •32-bitCPUcorecomplex(e200z650) –CompliantwithPowerArchitectureembeddedcategory –32KBunifiedcachewithlinelockingandeight-entry storebuffer16 –Executionspeedstaticto116MHz •32-bitI/Oprocessor(e200z0) –Executionspeedstaticto1/2CPUcores

ETC

MPC566MVR56

NXP 32-bit MCU, Power Arch core, 1MB Flash, 56MHz, -40/+125degC, Automotive Grade, PBGA 388; • Supports code compression\n• Three time processor units (TPU3) • TPU3_A and TPU3_B are connected to DPTRAM_AB (6 KB)\n• TPU3_C is connected to DPTRAM_C (4 KB)\n• A 22-timer channel modular I/O system (MIOS14) • Same as MIOS1 plus a real-time clock sub-module (MRTCSM), four counter sub-modules (MCSM), and four pulse width modulated (PWM) sub-modules (MPWMSM)\n• Three TouCAN modules (TOUCAN_A, TOUCAN_B, TOUCAN_C)\n• Two enhanced queued analog-to-digital converters (QADC64E_A, QADC64E_B) with up to 40 total analog channels. These modules are configured so each module can access all 40 of the analog inputs to the part (orthogonal)\n• Two queued serial multi-channel module (QSMCM_A, QSMCM_B), each of which contains a queued serial peripheral interface (QSPI) and two serial controller interfaces (SCI/UART)\n• A J1850 (DLCMD2) communications module\n• A NEXUS debug port (class 3) – IEEE®-ISTO 5001-1999\n• JTAG and background debug mode (BDM)\n;

The MPC566 integrates a Power Architecture® core with a dual precision floating point unit and BCC, 36 KB of RAM and 1 MB of flash memory.\nThe MPC566, an upgraded version of the MPC565, offers code compression to enable more efficient use of internal or external flash memory. Code compression is optimized for automotive (non-cached) applications and the new scheme increases performance by 40 to 50 percent.\n

恩XP

MPC566MZP56

NXP 32-bit MCU, Power Arch core, 1MB Flash, 56MHz, -40/+125degC, Automotive Grade, PBGA 388; • Supports code compression\n• Three time processor units (TPU3) • TPU3_A and TPU3_B are connected to DPTRAM_AB (6 KB)\n• TPU3_C is connected to DPTRAM_C (4 KB)\n• A 22-timer channel modular I/O system (MIOS14) • Same as MIOS1 plus a real-time clock sub-module (MRTCSM), four counter sub-modules (MCSM), and four pulse width modulated (PWM) sub-modules (MPWMSM)\n• Three TouCAN modules (TOUCAN_A, TOUCAN_B, TOUCAN_C)\n• Two enhanced queued analog-to-digital converters (QADC64E_A, QADC64E_B) with up to 40 total analog channels. These modules are configured so each module can access all 40 of the analog inputs to the part (orthogonal)\n• Two queued serial multi-channel module (QSMCM_A, QSMCM_B), each of which contains a queued serial peripheral interface (QSPI) and two serial controller interfaces (SCI/UART)\n• A J1850 (DLCMD2) communications module\n• A NEXUS debug port (class 3) – IEEE®-ISTO 5001-1999\n• JTAG and background debug mode (BDM)\n;

The MPC566 integrates a Power Architecture® core with a dual precision floating point unit and BCC, 36 KB of RAM and 1 MB of flash memory.\nThe MPC566, an upgraded version of the MPC565, offers code compression to enable more efficient use of internal or external flash memory. Code compression is optimized for automotive (non-cached) applications and the new scheme increases performance by 40 to 50 percent.\n

恩XP

MPC5668E

MPC5668x Microcontroller Data Sheet

MPC5668G

MPC5668x Microcontroller Data Sheet