Dual J-K Flip-Flops with Preset and Clear

文件：123.94 Kbytes 页数：4 Pages

NSCNational Semiconductor (TI)

美国国家半导体美国国家半导体公司

Dual J-K Flip-Flops with Preset and Clear

文件：123.94 Kbytes 页数：4 Pages

NSCNational Semiconductor (TI)

美国国家半导体美国国家半导体公司

Dual JK flip-flop with set and reset; positive-edge trigger

GENERAL DESCRIPTION The 74HC/HCT109 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT109 are dual positive-edge triggered, JK flip-flops with individual J, K inputs, clock (CP)

文件：65.67 Kbytes 页数：9 Pages

PHI

飞利浦

Dual JK flip-flop with set and reset; positive-edge-trigger

1. General description The 74HC109; 74HCT109 is a dual positive edge triggered JK flip-flop featuring individual J and K inputs, clock (CP) inputs, set (SD) and reset (RD) inputs and complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of

文件：271.64 Kbytes 页数：16 Pages

NEXPERIANexperia B.V. All rights reserved

安世安世半导体(中国)有限公司

Dual JK flip-flop with set and reset; positive-edge trigger

GENERAL DESCRIPTION The 74HC/HCT109 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT109 are dual positive-edge triggered, JK flip-flops with individual J, K inputs, clock (CP)

文件：65.67 Kbytes 页数：9 Pages

PHI

飞利浦