Dual J-K Flip-Flops with Preset and Clear

文件：136.2 Kbytes 页数：6 Pages

NSC

国半

Dual J-K Flip-Flops with Preset and Clear

General Description\nThese high speed (30 MHz minimum) J-K Flip-Flops utilize advanced silicon-gate CMOS technology to achieve, the low power consumption and high noise immunity of standard CMOS integrated circuits, along with the ability to drive 10 LS-TTL loads. ■ Typical propagation delay: 16 ns\n■ Wide operating voltage range\n■ Low input current: 1 mA maximum\n■ Low quiescent current: 40 mA maximum (74HC Series)\n■ High output drive: 10 LS-TTL loads ;

TI

德州仪器

Dual J-K Flip-Flops with Preset and Clear

文件：136.2 Kbytes 页数：6 Pages

NSC

国半

Dual J-K Flip-Flops with Preset and Clear

文件：136.2 Kbytes 页数：6 Pages

NSC

国半