Dual AND-OR-Invert Gate, Dual AND-OR Gate

General Description\nThese gates utilize advanced silicon-gate CMOS technology to achieve operating speeds similar to LS-TTL gates with the low power consumption of standard CMOS integrated circuits. All gates have buffered outputs, providing high noise immunity and the ability to drive 10 LS-TTL lo Typical propagation delay: 10 ns\nWide power supply range: 2± 6V\nLow quiescent supply current: 20mA maximum (74 Series)\nLow input current: 1mA maximum\nHigh output current: 4 mA minimum;

TI

德州仪器

Dual AND-OR-Invert Gate / Dual AND-OR Gate

文件：126.33 Kbytes 页数：4 Pages

NSCNational Semiconductor (TI)

美国国家半导体美国国家半导体公司

Dual AND-OR gate

GENERAL DESCRIPTION The 74HC58 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A. The “58” provides two sections of AND-OR gates. One section contains a 2-wide, 3-input (1A to 1F) AND-OR gate an

文件：35.92 Kbytes 页数：5 Pages

PHI

飞利浦

Dual AND-OR gate

GENERAL DESCRIPTION The 74HC58 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A. The “58” provides two sections of AND-OR gates. One section contains a 2-wide, 3-input (1A to 1F) AND-OR gate an

文件：35.92 Kbytes 页数：5 Pages

PHI

飞利浦

Dual AND-OR gate

GENERAL DESCRIPTION The 74HC58 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A. The “58” provides two sections of AND-OR gates. One section contains a 2-wide, 3-input (1A to 1F) AND-OR gate an

文件：35.92 Kbytes 页数：5 Pages

PHI

飞利浦