Dual AND-OR gate

GENERAL DESCRIPTION The 74HC58 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A. The “58” provides two sections of AND-OR gates. One section contains a 2-wide, 3-input (1A to 1F) AND-OR gate an

文件：35.92 Kbytes 页数：5 Pages

PHI

飞利浦

Dual AND-OR gate

GENERAL DESCRIPTION The 74HC58 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A. The “58” provides two sections of AND-OR gates. One section contains a 2-wide, 3-input (1A to 1F) AND-OR gate an

文件：35.92 Kbytes 页数：5 Pages

PHI

飞利浦

Dual AND-OR gate

GENERAL DESCRIPTION The 74HC58 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A. The “58” provides two sections of AND-OR gates. One section contains a 2-wide, 3-input (1A to 1F) AND-OR gate an

文件：35.92 Kbytes 页数：5 Pages

PHI

飞利浦

Dual AND-OR gate

GENERAL DESCRIPTION The 74HC58 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A. The “58” provides two sections of AND-OR gates. One section contains a 2-wide, 3-input (1A to 1F) AND-OR gate an

文件：35.92 Kbytes 页数：5 Pages

PHI

飞利浦

DUAL AND-OR GATES

General Description These device are identical in pinout to the 57/74ls58. they contain one 2-wide 2-input & one 2-wide 3-input AND-OR gates. These devices are characterized for operation over wide tmeperature ranges to meet industry and military specifications.

文件：169.3 Kbytes 页数：4 Pages

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