Dual AND-OR gate

GENERAL DESCRIPTION The 74HC58 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A. The “58” provides two sections of AND-OR gates. One section contains a 2-wide, 3-input (1A to 1F) AND-OR gate an

文件：35.92 Kbytes 页数：5 Pages

PHI

PHI

Dual AND-OR gate

GENERAL DESCRIPTION The 74HC58 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A. The “58” provides two sections of AND-OR gates. One section contains a 2-wide, 3-input (1A to 1F) AND-OR gate an

文件：35.92 Kbytes 页数：5 Pages

PHI

PHI

Dual AND-OR gate

GENERAL DESCRIPTION The 74HC58 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A. The “58” provides two sections of AND-OR gates. One section contains a 2-wide, 3-input (1A to 1F) AND-OR gate an

文件：35.92 Kbytes 页数：5 Pages

PHI

PHI

Dual AND-OR-Invert Gate / Dual AND-OR Gate

文件：126.33 Kbytes 页数：4 Pages

NSC

国半

Dual AND-OR-Invert Gate / Dual AND-OR Gate

文件：126.33 Kbytes 页数：4 Pages

NSC

国半